Commit missing parts of 7f914a0.

m-labs · Jan 10, 2016 · 63f7899 · 63f7899
1 parent 225f7d7
commit 63f7899
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/artiq/compiler/transforms/llvm_ir_generator.py b/artiq/compiler/transforms/llvm_ir_generator.py
@@ -191,6 +191,7 @@ def needs_sret(self, lltyp, may_be_large=True):
                 and len(lltyp.elements) <= 2:
             return not any([self.needs_sret(elt, may_be_large=False) for elt in lltyp.elements])
         else:
+            assert isinstance(lltyp, ll.Type)
             return True
 
     def has_sret(self, functy):
@@ -1239,7 +1240,7 @@ def process_Return(self, insn):
             return self.llbuilder.ret_void()
         else:
             llvalue = self.map(insn.value())
-            if self.needs_sret(llvalue):
+            if self.needs_sret(llvalue.type):
                 self.llbuilder.store(llvalue, self.llfunction.args[0])
                 return self.llbuilder.ret_void()
             else: