test/coredevice/portability: keep trace list entirely on host.

m-labs · Dec 31, 2015 · cb90bf6 · cb90bf6
1 parent a2618f0
commit cb90bf6
Showing 1 changed file with 14 additions and 11 deletions.
diff --git a/artiq/test/coredevice/portability.py b/artiq/test/coredevice/portability.py
@@ -118,43 +118,46 @@ def build(self):
         self.setattr_device("core")
         self.setattr_argument("trace")
 
+    def _trace(self, i):
+        self.trace.append(i)
+
     @kernel
     def run(self):
         for i in range(10):
-            self.trace.append(i)
+            self._trace(i)
             if i == 4:
                 try:
-                    self.trace.append(10)
+                    self._trace(10)
                     try:
-                        self.trace.append(11)
+                        self._trace(11)
                         break
                     except:
                         pass
                     else:
-                        self.trace.append(12)
+                        self._trace(12)
                     try:
-                        self.trace.append(13)
+                        self._trace(13)
                     except:
                         pass
                 except _MyException:
-                    self.trace.append(14)
+                    self._trace(14)
 
         for i in range(4):
             try:
-                self.trace.append(100)
+                self._trace(100)
                 if i == 1:
                     raise _MyException()
                 elif i == 2:
                     raise IndexError()
             except IndexError:
-                self.trace.append(101)
+                self._trace(101)
                 raise
             except:
-                self.trace.append(102)
+                self._trace(102)
             else:
-                self.trace.append(103)
+                self._trace(103)
             finally:
-                self.trace.append(104)
+                self._trace(104)
 
 
 class _RPCExceptions(EnvExperiment):