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litesata/example_designs: fix core generation (RAID introduced some c…
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…hanges on the PHY)
enjoy-digital committed Jun 25, 2015
1 parent c615b50 commit 04c64eb
Showing 3 changed files with 14 additions and 8 deletions.
Original file line number Diff line number Diff line change
@@ -4,14 +4,15 @@
_io = [
("sys_clk", 0, Pins("X")),
("sys_rst", 1, Pins("X")),

("sata_clocks", 0,
Subsignal("refclk_p", Pins("X")),
Subsignal("refclk_n", Pins("X")),
),
("sata", 0,
Subsignal("refclk_p", Pins("C8")),
Subsignal("refclk_n", Pins("C7")),
Subsignal("txp", Pins("D2")),
Subsignal("txn", Pins("D1")),
Subsignal("rxp", Pins("E4")),
Subsignal("rxn", Pins("E3")),
Subsignal("txp", Pins("X")),
Subsignal("txn", Pins("X")),
Subsignal("rxp", Pins("X")),
Subsignal("rxn", Pins("X")),
),
]

6 changes: 5 additions & 1 deletion misoclib/mem/litesata/example_designs/targets/core.py
Original file line number Diff line number Diff line change
@@ -17,7 +17,7 @@ def __init__(self, platform, clk_freq=166*1000000, with_bist=True, nports=4):
self.clk_freq = clk_freq

# SATA PHY/Core/Frontend
self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sys_clk"), platform.request("sata"), "sata_gen2", clk_freq)
self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata"), "sata_gen2", clk_freq)
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)

@@ -32,6 +32,10 @@ def get_ios(self):
ios = set()

# Transceiver
for e in dir(self.sata_phy.clock_pads):
obj = getattr(self.sata_phy.clock_pads, e)
if isinstance(obj, Signal):
ios = ios.union({obj})
for e in dir(self.sata_phy.pads):
obj = getattr(self.sata_phy.pads, e)
if isinstance(obj, Signal):
1 change: 1 addition & 0 deletions misoclib/mem/litesata/phy/__init__.py
Original file line number Diff line number Diff line change
@@ -5,6 +5,7 @@

class LiteSATAPHY(Module):
def __init__(self, device, clock_pads_or_refclk, pads, revision, clk_freq):
self.clock_pads = clock_pads_or_refclk
self.pads = pads
self.revision = revision

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