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pipistrello: drop rtio fifos for invisible leds
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the main board leds are all under the adapter board

also tweak fifo depths a bit in a feeble attempt to circumvent a ISE hang (par
phase 4)
jordens committed Jun 29, 2015
1 parent e2cb0e1 commit 165ef20
Showing 1 changed file with 1 addition and 5 deletions.
6 changes: 1 addition & 5 deletions soc/targets/artiq_pipistrello.py
Original file line number Diff line number Diff line change
@@ -105,12 +105,8 @@ def __init__(self, platform, cpu_type="or1k", **kwargs):

phy = ttl_simple.Output(platform.request("ext_led", 0))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256))

for i in range(2, 5):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))

self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))

2 comments on commit 165ef20

@sbourdeauducq
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Can we keep one? It would be useful for quick checks without the adapter board.

@jordens
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Ack.

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