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  • 5 commits
  • 12 files changed
  • 1 contributor

Commits on Jun 29, 2015

  1. language: allow experiments to import from artiq.language

    this way the import stanza shows what is imported: just experiment language
    related components
    
    keep the imports also at top level until experiments have transitioned
    
    the top level __init__.py should build and expose the entire namespace of artiq
    related things, like hdf5 analysis tools, frontend components (like experiment
    running api), deployment tools etc.
    jordens committed Jun 29, 2015
    5
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    39e9e73 View commit details
  2. test: hardware testbench

    jordens committed Jun 29, 2015
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    f7427dd View commit details
  4. benchmarks/*: remove

    Benchmarks should be shaped as unittests and run as part of CI.
    jordens committed Jun 29, 2015
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    5442ae3 View commit details
  5. pipistrello: add notes to nist_qc1 about dds_clock

    * remove xtrig from the target as it is not usually connected (used for
      dds_clock) and ignore PMT2/BTN2 as C:15 is used for dds_clock.
    * this also aligns the ttl channel numbers with kc705/nist_qc1 (two pmt
      inputs followed by 16 ttl outputs followed by leds)
    jordens committed Jun 29, 2015
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6 changes: 2 additions & 4 deletions artiq/__init__.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,2 @@
from artiq.language.core import *
from artiq.language.experiment import Experiment
from artiq.language.db import *
from artiq.language.units import *
from artiq import language
from artiq.language import *
16 changes: 14 additions & 2 deletions artiq/gateware/nist_qc1.py
Original file line number Diff line number Diff line change
@@ -4,10 +4,22 @@
papilio_adapter_io = [
("ext_led", 0, Pins("B:7"), IOStandard("LVTTL")),

# to feed the 125 MHz clock (preferrably from DDS SYNC_CLK)
# to the FPGA, use the xtrig pair.
#
# on papiliopro-adapter, xtrig (C:12) is connected to a GCLK
#
# on pipistrello, C:15 is the only GCLK in proximity, used as a button
# input, BTN2/PMT2 in papiliopro-adapter
# either improve the DDS box to feed 125MHz into the PMT2 pair, or:
#
# * disconnect C:15 from its periphery on the adapter board
# * bridge C:15 to the xtrig output of the transciever
# * optionally, disconnect C:12 from its periphery
("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")),
("pmt", 0, Pins("C:13"), IOStandard("LVTTL")),
("pmt", 1, Pins("C:14"), IOStandard("LVTTL")),
("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")),
("dds_clock", 0, Pins("C:15"), IOStandard("LVTTL")), # PMT2
("pmt", 2, Pins("C:15"), IOStandard("LVTTL")), # rarely equipped

("ttl", 0, Pins("C:11"), IOStandard("LVTTL")),
("ttl", 1, Pins("C:10"), IOStandard("LVTTL")),
4 changes: 4 additions & 0 deletions artiq/language/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,4 @@
from artiq.language.core import *
from artiq.language.experiment import Experiment
from artiq.language.db import *
from artiq.language.units import *
120 changes: 120 additions & 0 deletions artiq/test/coredevice.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,120 @@
from math import sqrt

from artiq.language import *
from artiq.test.hardware_testbench import ExperimentCase
from artiq.coredevice.runtime_exceptions import RTIOUnderflow


class RTT(Experiment, AutoDB):
class DBKeys:
core = Device()
ttl_inout = Device()
rtt = Result()

@kernel
def run(self):
self.ttl_inout.output()
delay(1*us)
with parallel:
self.ttl_inout.gate_rising(2*us)
with sequential:
delay(1*us)
t0 = now()
self.ttl_inout.pulse(1*us)
self.rtt = self.ttl_inout.timestamp() - t0


class Loopback(Experiment, AutoDB):
class DBKeys:
core = Device()
loop_in = Device()
loop_out = Device()
rtt = Result()

@kernel
def run(self):
with parallel:
self.loop_in.gate_rising(2*us)
with sequential:
delay(1*us)
t0 = now()
self.loop_out.pulse(1*us)
self.rtt = self.loop_in.timestamp() - t0


class PulseRate(Experiment, AutoDB):
class DBKeys:
core = Device()
loop_out = Device()
pulse_rate = Result()

@kernel
def run(self):
dt = time_to_cycles(1000*ns)
while True:
try:
for i in range(1000):
self.loop_out.pulse(cycles_to_time(dt))
delay(cycles_to_time(dt))
except RTIOUnderflow:
dt += 1
self.core.break_realtime()
else:
self.pulse_rate = cycles_to_time(2*dt)
break


class CoredeviceTest(ExperimentCase):
def test_rtt(self):
rtt = self.execute(RTT)["rtt"]
print(rtt)
self.assertGreater(rtt, 0*ns)
self.assertLess(rtt, 100*ns)

def test_loopback(self):
rtt = self.execute(Loopback)["rtt"]
print(rtt)
self.assertGreater(rtt, 0*ns)
self.assertLess(rtt, 40*ns)

def test_pulse_rate(self):
rate = self.execute(PulseRate)["pulse_rate"]
print(rate)
self.assertGreater(rate, 100*ns)
self.assertLess(rate, 2500*ns)


class RPCTiming(Experiment, AutoDB):
class DBKeys:
core = Device()
repeats = Argument(100)
rpc_time_mean = Result()
rpc_time_stddev = Result()

def nop(self, x):
pass

@kernel
def bench(self):
self.ts = [0. for _ in range(self.repeats)]
for i in range(self.repeats):
t1 = self.core.get_rtio_time()
self.nop(1)
t2 = self.core.get_rtio_time()
self.ts[i] = t2 - t1

def run(self):
self.bench()
mean = sum(self.ts)/self.repeats
self.rpc_time_stddev = sqrt(
sum([(t - mean)**2 for t in self.ts])/self.repeats)*s
self.rpc_time_mean = mean*s


class RPCTest(ExperimentCase):
def test_rpc_timing(self):
res = self.execute(RPCTiming)
print(res)
self.assertGreater(res["rpc_time_mean"], 100*ns)
self.assertLess(res["rpc_time_mean"], 10*ms)
self.assertLess(res["rpc_time_stddev"], 1*ms)
43 changes: 43 additions & 0 deletions artiq/test/hardware_testbench.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
import os
import sys
import unittest
import logging

from artiq.language import *
from artiq.protocols.file_db import FlatFileDB
from artiq.master.worker_db import DBHub, ResultDB
from artiq.frontend.artiq_run import (
DummyScheduler, DummyWatchdog, SimpleParamLogger)


artiq_root = os.getenv("ARTIQ_ROOT")
logger = logging.getLogger(__name__)


@unittest.skipUnless(artiq_root, "no ARTIQ_ROOT")
class ExperimentCase(unittest.TestCase):
def setUp(self):
self.ddb = FlatFileDB(os.path.join(artiq_root, "ddb.pyon"))
self.pdb = FlatFileDB(os.path.join(artiq_root, "pdb.pyon"))
self.rdb = ResultDB(lambda description: None, lambda mod: None)
self.dbh = DBHub(self.ddb, self.pdb, self.rdb)

def execute(self, cls, **kwargs):
expid = {
"file": sys.modules[cls.__module__].__file__,
"experiment": cls.__name__,
"arguments": kwargs
}
sched = DummyScheduler(expid)
try:
try:
exp = cls(self.dbh, scheduler=sched, **kwargs)
except KeyError as e:
# skip if ddb does not match requirements
raise unittest.SkipTest(*e.args)
self.rdb.build()
exp.run()
exp.analyze()
return self.rdb.data.read
finally:
self.dbh.close_devices()
18 changes: 0 additions & 18 deletions benchmarks/all.py

This file was deleted.

28 changes: 0 additions & 28 deletions benchmarks/ddb.pyon

This file was deleted.

1 change: 0 additions & 1 deletion benchmarks/pdb.pyon

This file was deleted.

26 changes: 0 additions & 26 deletions benchmarks/pulse_rate.py

This file was deleted.

32 changes: 0 additions & 32 deletions benchmarks/rpc_timing.py

This file was deleted.

29 changes: 0 additions & 29 deletions benchmarks/rtio_skew.py

This file was deleted.

10 changes: 6 additions & 4 deletions soc/targets/artiq_pipistrello.py
Original file line number Diff line number Diff line change
@@ -34,7 +34,7 @@ def __init__(self, platform, clk_freq):
i_FREEZEDCM=0,
i_RST=ResetSignal())

rtio_external_clk = platform.request("dds_clock")
rtio_external_clk = platform.request("pmt", 2)
platform.add_period_constraint(rtio_external_clk, 8.0)
self.specials += Instance("BUFGMUX",
i_I0=rtio_internal_clk,
@@ -95,11 +95,13 @@ def __init__(self, platform, cpu_type="or1k", **kwargs):
for i in range(2):
phy = ttl_simple.Inout(platform.request("pmt", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512,
ofifo_depth=4))

phy = ttl_simple.Inout(platform.request("xtrig", 0))
phy = ttl_simple.Inout(platform.request("xtrig"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4,
ofifo_depth=4))

for i in range(16):
phy = ttl_simple.Output(platform.request("ttl", i))