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base repository: m-labs/artiq
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compare: d1c4cf0b78e7
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Jun 29, 2015

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Showing with 24 additions and 14 deletions.
  1. +18 −14 doc/manual/fpga_board_ports.rst
  2. +6 −0 soc/targets/artiq_pipistrello.py
32 changes: 18 additions & 14 deletions doc/manual/fpga_board_ports.rst
Original file line number Diff line number Diff line change
@@ -13,20 +13,24 @@ The low-cost Pipistrello FPGA board can be used as a lower-cost but slower alter

When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are mapped to RTIO channels as follows:

+--------------+----------+-----------------+
| RTIO channel | TTL line | Capability |
+==============+==========+=================+
| 0 | PMT0 | Input only |
+--------------+----------+-----------------+
| 1 | PMT1 | Input only |
+--------------+----------+-----------------+
| 2-18 | TTL0-16 | Output only |
+--------------+----------+-----------------+
| 19-21 | LEDs | Output only |
+--------------+----------+-----------------+
| 22 | TTL2 | Output only |
+--------------+----------+-----------------+
+--------------+----------+------------+
| RTIO channel | TTL line | Capability |
+==============+==========+============+
| 0 | PMT0 | Input |
+--------------+----------+------------+
| 1 | PMT1 | Input |
+--------------+----------+------------+
| 2-17 | TTL0-15 | Output |
+--------------+----------+------------+
| 18 | EXT_LED | Output |
+--------------+----------+------------+
| 19 | USER_LED | Output |
+--------------+----------+------------+
| 20 | DDS | Output |
+--------------+----------+------------+

The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Pipistrello board), the corresponding pins on the Pipistrello can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention.

The board can accept an external RTIO clock connected to PMT2.
The board can accept an external RTIO clock connected to PMT2. If the DDS box
does not drive the PMT2 pair, use XTRIG and patch the XTRIG transciever output
on the adapter board onto C:15 disconnecting PMT2.
6 changes: 6 additions & 0 deletions soc/targets/artiq_pipistrello.py
Original file line number Diff line number Diff line change
@@ -83,6 +83,8 @@ def __init__(self, platform, cpu_type="or1k", **kwargs):
self.submodules.leds = gpio.GPIOOut(Cat(
platform.request("user_led", 0),
platform.request("user_led", 1),
platform.request("user_led", 2),
platform.request("user_led", 3),
))

self.comb += [
@@ -107,6 +109,10 @@ def __init__(self, platform, cpu_type="or1k", **kwargs):
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))

phy = ttl_simple.Output(platform.request("user_led", 4))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))

self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))

self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))