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sdram/module: cleanup indent
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@enjoy-digital
enjoy-digital committed Aug 20, 2015
1 parent 63538a7 commit 4acab79
Showing 1 changed file with 63 additions and 63 deletions.
126 changes: 63 additions & 63 deletions misoclib/mem/sdram/module.py
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Expand Up @@ -48,18 +48,18 @@ def ns(self, t, margin=True):
# SDR
class IS42S16160(SDRAMModule):
geom_settings = {
"nbanks": 4,
"nrows": 8192,
"ncols": 512
"nbanks": 4,
"nrows": 8192,
"ncols": 512
}
# Note: timings for -7 speedgrade (add support for others speedgrades)
timing_settings = {
"tRP": 20,
"tRCD": 20,
"tWR": 20,
"tWTR": 2,
"tREFI": 64*1000*1000/8192,
"tRFC": 70
"tRP": 20,
"tRCD": 20,
"tWR": 20,
"tWTR": 2,
"tREFI": 64*1000*1000/8192,
"tRFC": 70
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
Expand All @@ -68,17 +68,17 @@ def __init__(self, clk_freq):

class MT48LC4M16(SDRAMModule):
geom_settings = {
"nbanks": 4,
"nrows": 4096,
"ncols": 256
"nbanks": 4,
"nrows": 4096,
"ncols": 256
}
timing_settings = {
"tRP": 15,
"tRCD": 15,
"tWR": 14,
"tWTR": 2,
"tREFI": 64*1000*1000/4096,
"tRFC": 66
"tRP": 15,
"tRCD": 15,
"tWR": 14,
"tWTR": 2,
"tREFI": 64*1000*1000/4096,
"tRFC": 66
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
Expand All @@ -87,18 +87,18 @@ def __init__(self, clk_freq):

class AS4C16M16(SDRAMModule):
geom_settings = {
"nbanks": 4,
"nrows": 8192,
"ncols": 512
"nbanks": 4,
"nrows": 8192,
"ncols": 512
}
# Note: timings for -6 speedgrade (add support for others speedgrades)
timing_settings = {
"tRP": 18,
"tRCD": 18,
"tWR": 12,
"tWTR": 2,
"tREFI": 64*1000*1000/8192,
"tRFC": 60
"tRP": 18,
"tRCD": 18,
"tWR": 12,
"tWTR": 2,
"tREFI": 64*1000*1000/8192,
"tRFC": 60
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
Expand All @@ -108,17 +108,17 @@ def __init__(self, clk_freq):
# DDR
class MT46V32M16(SDRAMModule):
geom_settings = {
"nbanks": 4,
"nrows": 8192,
"ncols": 1024
"nbanks": 4,
"nrows": 8192,
"ncols": 1024
}
timing_settings = {
"tRP": 15,
"tRCD": 15,
"tWR": 15,
"tWTR": 2,
"tREFI": 64*1000*1000/8192,
"tRFC": 70
"tRP": 15,
"tRCD": 15,
"tWR": 15,
"tWTR": 2,
"tREFI": 64*1000*1000/8192,
"tRFC": 70
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR", self.geom_settings,
Expand All @@ -128,17 +128,17 @@ def __init__(self, clk_freq):
# LPDDR
class MT46H32M16(SDRAMModule):
geom_settings = {
"nbanks": 4,
"nrows": 8192,
"ncols": 1024
"nbanks": 4,
"nrows": 8192,
"ncols": 1024
}
timing_settings = {
"tRP": 15,
"tRCD": 15,
"tWR": 15,
"tWTR": 2,
"tREFI": 64*1000*1000/8192,
"tRFC": 72
"tRP": 15,
"tRCD": 15,
"tWR": 15,
"tWTR": 2,
"tREFI": 64*1000*1000/8192,
"tRFC": 72
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "LPDDR", self.geom_settings,
Expand All @@ -148,17 +148,17 @@ def __init__(self, clk_freq):
# DDR2
class MT47H128M8(SDRAMModule):
geom_settings = {
"nbanks": 8,
"nrows": 16384,
"ncols": 1024
"nbanks": 8,
"nrows": 16384,
"ncols": 1024
}
timing_settings = {
"tRP": 15,
"tRCD": 15,
"tWR": 15,
"tWTR": 2,
"tREFI": 7800,
"tRFC": 127.5
"tRP": 15,
"tRCD": 15,
"tWR": 15,
"tWTR": 2,
"tREFI": 7800,
"tRFC": 127.5
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
Expand All @@ -168,17 +168,17 @@ def __init__(self, clk_freq):
# DDR3
class MT8JTF12864(SDRAMModule):
geom_settings = {
"nbanks": 8,
"nrows": 16384,
"ncols": 1024
"nbanks": 8,
"nrows": 16384,
"ncols": 1024
}
timing_settings = {
"tRP": 15,
"tRCD": 15,
"tWR": 15,
"tWTR": 2,
"tREFI": 7800,
"tRFC": 70
"tRP": 15,
"tRCD": 15,
"tWR": 15,
"tWTR": 2,
"tREFI": 7800,
"tRFC": 70
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
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