coredevice/TTLClockGen: fix attribute init

sbourdeauducq · sbourdeauducq · commit 1991b3c91051 · 2015-08-27T09:48:11.000+08:00
diff --git a/artiq/coredevice/ttl.py b/artiq/coredevice/ttl.py
@@ -220,7 +220,6 @@ def __init__(self, dmgr, channel):
         self.core = dmgr.get("core")
         self.channel = channel
 
-    def build(self):
         # in RTIO cycles
         self.previous_timestamp = int64(0)
         self.acc_width = 24
