coredevice/TTLClockGen: fix attribute init

m-labs · Aug 27, 2015 · 1991b3c · 1991b3c
1 parent 4cb0d45
commit 1991b3c
Showing 1 changed file with 0 additions and 1 deletion.
diff --git a/artiq/coredevice/ttl.py b/artiq/coredevice/ttl.py
@@ -220,7 +220,6 @@ def __init__(self, dmgr, channel):
         self.core = dmgr.get("core")
         self.channel = channel
 
-    def build(self):
         # in RTIO cycles
         self.previous_timestamp = int64(0)
         self.acc_width = 24