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coredevice/TTLClockGen: fix attribute init
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sbourdeauducq committed Aug 27, 2015

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makenowjust Hiroya Fujinami
1 parent 4cb0d45 commit 1991b3c
Showing 1 changed file with 0 additions and 1 deletion.
1 change: 0 additions & 1 deletion artiq/coredevice/ttl.py
Original file line number Diff line number Diff line change
@@ -220,7 +220,6 @@ def __init__(self, dmgr, channel):
self.core = dmgr.get("core")
self.channel = channel

def build(self):
# in RTIO cycles
self.previous_timestamp = int64(0)
self.acc_width = 24

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