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base repository: m-labs/artiq
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compare: 0fe0f4d433ad
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  • 2 commits
  • 4 files changed
  • 1 contributor

Commits on Aug 27, 2015

  1. runtime/dds: fix AD9914 register initialization values 

    Thanks Raghavendra Srinivas for the help. Closes #114.
    @sbourdeauducq
    sbourdeauducq committed Aug 27, 2015

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    f07c7e9 View commit details

  2. dds: fix phase computation. Closes #79.

    @sbourdeauducq
    sbourdeauducq committed Aug 27, 2015

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Showing with 9 additions and 4 deletions.
  1. +3 −3 artiq/coredevice/dds.py
  2. +3 −1 soc/runtime/dds.c
  3. +1 −0 soc/runtime/dds.h
  4. +2 −0 soc/runtime/test_mode.c
6 changes: 3 additions & 3 deletions artiq/coredevice/dds.py
View file
Original file line number Diff line number Diff line change
@@ -131,11 +131,11 @@ def set_mu(self, frequency, phase=0, phase_mode=_PHASE_MODE_DEFAULT):
"""
if phase_mode == _PHASE_MODE_DEFAULT:
phase_mode = self.phase_mode
syscall("dds_set", now_mu(), self.channel,
frequency, round(phase*2**self.pow_width), phase_mode)
syscall("dds_set", now_mu(), self.channel, frequency,
phase, phase_mode)

@kernel
def set(self, frequency, phase=0, phase_mode=_PHASE_MODE_DEFAULT):
def set(self, frequency, phase=0.0, phase_mode=_PHASE_MODE_DEFAULT):
"""Like ``set_mu``, but uses Hz and turns."""
self.set_mu(self.frequency_to_ftw(frequency),
self.turns_to_pow(phase), phase_mode)
4 changes: 3 additions & 1 deletion soc/runtime/dds.c
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Original file line number Diff line number Diff line change
@@ -18,7 +18,7 @@
/* DAC calibration takes max. 135us as per datasheet. Take a good margin. */
#define DURATION_DAC_CAL (30000 << RTIO_FINE_TS_WIDTH)
/* not counting final FUD */
#define DURATION_INIT (8*DURATION_WRITE + DURATION_DAC_CAL)
#define DURATION_INIT (10*DURATION_WRITE + DURATION_DAC_CAL)
#define DURATION_PROGRAM (5*DURATION_WRITE) /* not counting FUD */

#else
@@ -79,6 +79,8 @@ void dds_init(long long int timestamp, int channel)
#ifdef DDS_AD9914
DDS_WRITE(DDS_CFR1H, 0x0000); /* Enable cosine output */
DDS_WRITE(DDS_CFR2L, 0x8900); /* Enable matched latency */
DDS_WRITE(DDS_CFR2H, 0x0080); /* Enable profile mode */
DDS_WRITE(DDS_ASF, 0x0fff); /* Set amplitude to maximum */
DDS_WRITE(DDS_CFR4H, 0x0105); /* Enable DAC calibration */
DDS_WRITE(DDS_FUD, 0);
now += DURATION_DAC_CAL;
1 change: 1 addition & 0 deletions soc/runtime/dds.h
View file
Original file line number Diff line number Diff line change
@@ -35,6 +35,7 @@
#define DDS_FTWL 0x2d
#define DDS_FTWH 0x2f
#define DDS_POW 0x31
#define DDS_ASF 0x33
#define DDS_FUD 0x80
#define DDS_GPIO 0x81
#endif
2 changes: 2 additions & 0 deletions soc/runtime/test_mode.c
View file
Original file line number Diff line number Diff line change
@@ -239,6 +239,8 @@ static void ddsinit(void)
brg_ddsreset();
brg_ddswrite(DDS_CFR1H, 0x0000); /* Enable cosine output */
brg_ddswrite(DDS_CFR2L, 0x8900); /* Enable matched latency */
brg_ddswrite(DDS_CFR2H, 0x0080); /* Enable profile mode */
brg_ddswrite(DDS_ASF, 0x0fff); /* Set amplitude to maximum */
brg_ddswrite(DDS_CFR4H, 0x0105); /* Enable DAC calibration */
brg_ddswrite(DDS_FUD, 0);
t = clock_get_ms();