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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: fba05531f456
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  • 2 commits
  • 4 files changed
  • 1 contributor

Commits on Aug 22, 2015

  1. qc2: DDS selection is active low

    @sbourdeauducq
    sbourdeauducq committed Aug 22, 2015
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    094fc1c View commit details

  2. runtime: enable ad9914 matched latency

    @sbourdeauducq
    sbourdeauducq committed Aug 22, 2015
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    fba0553 View commit details
Showing with 15 additions and 18 deletions.
  1. +4 −1 artiq/gateware/ad9xxx.py
  2. +3 −3 artiq/gateware/nist_qc2.py
  3. +4 −10 soc/runtime/dds.c
  4. +4 −4 soc/runtime/test_mode.c
5 changes: 4 additions & 1 deletion artiq/gateware/ad9xxx.py
View file
Original file line number Diff line number Diff line change
@@ -62,7 +62,10 @@ def __init__(self, pads,
self.comb += pads.rst.eq(gpio[0])
else:
self.comb += pads.rst_n.eq(~gpio[0])
self.comb += pads.sel.eq(gpio[1:])
if hasattr(pads, "sel"):
self.comb += pads.sel.eq(gpio[1:])
else:
self.comb += pads.sel_n.eq(~gpio[1:])

bus_r_gpio = Signal()
self.comb += If(bus_r_gpio,
6 changes: 3 additions & 3 deletions artiq/gateware/nist_qc2.py
View file
Original file line number Diff line number Diff line change
@@ -26,9 +26,9 @@
"LPC:LA11_N LPC:LA12_N LPC:LA11_P LPC:LA12_P "
"LPC:LA07_N LPC:LA08_N LPC:LA07_P LPC:LA08_P "
"LPC:LA04_N LPC:LA03_N LPC:LA04_P LPC:LA03_P")),
Subsignal("sel", Pins("LPC:LA24_N LPC:LA29_P LPC:LA28_P LPC:LA29_N "
"LPC:LA28_N LPC:LA31_P LPC:LA30_P LPC:LA31_N "
"LPC:LA30_N LPC:LA33_P LPC:LA33_N")),
Subsignal("sel_n", Pins("LPC:LA24_N LPC:LA29_P LPC:LA28_P LPC:LA29_N "
"LPC:LA28_N LPC:LA31_P LPC:LA30_P LPC:LA31_N "
"LPC:LA30_N LPC:LA33_P LPC:LA33_N")),
Subsignal("fud", Pins("LPC:LA21_N")),
Subsignal("wr_n", Pins("LPC:LA24_P")),
Subsignal("rd_n", Pins("LPC:LA25_N")),
14 changes: 4 additions & 10 deletions soc/runtime/dds.c
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Original file line number Diff line number Diff line change
@@ -77,18 +77,12 @@ void dds_init(long long int timestamp, int channel)
#endif

#ifdef DDS_AD9914
/*
* Enable cosine output (to match AD9858 behavior)
* Enable DAC calibration
* Leave SYNCLK enabled and PLL/divider disabled
*/
DDS_WRITE(DDS_CFR1L, 0x0008);
DDS_WRITE(DDS_CFR1H, 0x0000);
DDS_WRITE(DDS_CFR4H, 0x0105);
DDS_WRITE(DDS_CFR1H, 0x0000); /* Enable cosine output */
DDS_WRITE(DDS_CFR2L, 0x8900); /* Enable matched latency */
DDS_WRITE(DDS_CFR4H, 0x0105); /* Enable DAC calibration */
DDS_WRITE(DDS_FUD, 0);
/* Disable DAC calibration */
now += DURATION_DAC_CAL;
DDS_WRITE(DDS_CFR4H, 0x0005);
DDS_WRITE(DDS_CFR4H, 0x0005); /* Disable DAC calibration */
DDS_WRITE(DDS_FUD, 0);
#endif
}
8 changes: 4 additions & 4 deletions soc/runtime/test_mode.c
View file
Original file line number Diff line number Diff line change
@@ -237,13 +237,13 @@ static void ddsinit(void)
long long int t;

brg_ddsreset();
brg_ddswrite(DDS_CFR1L, 0x0008);
brg_ddswrite(DDS_CFR1H, 0x0000);
brg_ddswrite(DDS_CFR4H, 0x0105);
brg_ddswrite(DDS_CFR1H, 0x0000); /* Enable cosine output */
brg_ddswrite(DDS_CFR2L, 0x8900); /* Enable matched latency */
brg_ddswrite(DDS_CFR4H, 0x0105); /* Enable DAC calibration */
brg_ddswrite(DDS_FUD, 0);
t = clock_get_ms();
while(clock_get_ms() < t + 2);
brg_ddswrite(DDS_CFR4H, 0x0005);
brg_ddswrite(DDS_CFR4H, 0x0005); /* Disable DAC calibration */
brg_ddsfud();
}
#endif