sdram/phy/s6ddrphy: fix comment on S6QuarterRateDDRPHY

enjoy-digital · enjoy-digital · commit a1e4183b3f19 · 2015-08-22T12:50:41.000+02:00
diff --git a/misoclib/mem/sdram/phy/s6ddrphy.py b/misoclib/mem/sdram/phy/s6ddrphy.py
@@ -428,7 +428,7 @@ def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
         self.clk8x_rd_strb = half_rate_phy.clk4x_rd_strb
 
         # sys_clk      : system clk, used for dfi interface
-        # sys2x_clk    : half rate  sys clk
+        # sys2x_clk    : 2x system clk
         sd_sys = getattr(self.sync, "sys")
         sd_sys2x = getattr(self.sync, "sys2x")
 
