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base repository: m-labs/misoc
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  • 5 commits
  • 6 files changed
  • 1 contributor

Commits on Aug 22, 2015

  1. README: small update

    @enjoy-digital
    enjoy-digital committed Aug 22, 2015
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    b8f3fd5 View commit details

  2. sdram/phy/s6ddrphy: rename S6DDRPHY to S6HalfRateDDRPHY and use ORed … 

    …wrdata_en/rddata_en (the controller already manages that)
    @enjoy-digital
    enjoy-digital committed Aug 22, 2015
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  3. liteeth/phy: fix autodetect (clk_freq not necessary passed in kwargs)

    @enjoy-digital
    enjoy-digital committed Aug 22, 2015
    3
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  4. sdram/phy/s6ddrphy: add S6QuarterRateDDRPHY to run DDR3 at higher fre… 

    …quencies.

Built on top of S6HalfRateDDRPHY, exposes a 4 phases DFI interface to the controller with a 2x slower clock.
Validated on the Numato Lab opsis board (50MHz sys_clk/ DDR400), should also work on the Novena laptop (same DDR3 module).
    @enjoy-digital
    enjoy-digital committed Aug 22, 2015
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  5. sdram/module: add P3R1GE4JGF DDR2 (Atlys) and MT41J128M16 DDR3 (Opsis… 

    …, Novena) modules.
    @enjoy-digital
    enjoy-digital committed Aug 22, 2015
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