@@ -77,21 +77,21 @@ def __init__(self, dw):
77
77
78
78
# # #
79
79
80
- self .buffer = Buffer (self .sink .description )
81
- self .comb += Record .connect (self .sink , self .buffer .sink )
80
+ self .submodules . buffer = Buffer (self .sink .description )
81
+ self .comb += Record .connect (self .sink , self .buffer .d )
82
82
83
83
rising = Signal (dw )
84
- rising .eq (self .rising_mask & sink .data & ~ self .buffer .source .data )
84
+ rising .eq (self .rising_mask & sink .data & ~ self .buffer .q .data )
85
85
86
86
falling = Signal (dw )
87
- falling .eq (self .falling_mask & sink .data & ~ self .buffer .source .data )
87
+ falling .eq (self .falling_mask & ~ sink .data & self .buffer .q .data )
88
88
89
89
both = Signal (dw )
90
- both .eq (self .both_mask & sink . data & ~ self . buffer . source . data )
90
+ both .eq (self .both_mask & ( rising | falling ) )
91
91
92
92
self .comb += [
93
- source .stb .eq (sink .stb & self .buffer .source .stb ),
94
- self .buffer .source .ack .eq (source .ack ),
93
+ source .stb .eq (sink .stb & self .buffer .q .stb ),
94
+ self .buffer .q .ack .eq (source .ack ),
95
95
source .hit .eq (rising | falling | both )
96
96
]
97
97
@@ -106,7 +106,7 @@ def __init__(self, dw):
106
106
# # #
107
107
108
108
self .comb += [
109
- self .rising .eq (self ._rising .storage ),
110
- self .falling .eq (self ._falling .storage ),
111
- self .both .eq (self ._both .storage )
109
+ self .rising_mask .eq (self ._rising .storage ),
110
+ self .falling_mask .eq (self ._falling .storage ),
111
+ self .both_mask .eq (self ._both .storage )
112
112
]
0 commit comments