kc705: fix ttl15

sbourdeauducq · sbourdeauducq · commit 0a9f9093f74d · 2015-07-02T20:02:05.000+02:00
diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py
@@ -129,7 +129,7 @@ def __init__(self, platform, cpu_type="or1k", **kwargs):
         for i in range(16):
             if i == 14:
                 # TTL14 is for the clock generator
-                break
+                continue
             if i % 4 == 3:
                 phy = ttl_simple.Inout(platform.request("ttl", i))
                 self.submodules += phy
