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  • 2 commits
  • 4 files changed
  • 1 contributor

Commits on Jul 5, 2015

  1. liteeth/core/mac: adapt depth on AsyncFIFOs according to phy (reduce … 

    …ressource usage with MII phy)
    @enjoy-digital
    enjoy-digital committed Jul 5, 2015

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    makenowjust Hiroya Fujinami
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    c100ef6 View commit details

  2. use sets for leave_out

    @enjoy-digital
    enjoy-digital committed Jul 5, 2015

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    chris-huxtable Chris Huxtable
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9 changes: 7 additions & 2 deletions misoclib/com/liteeth/core/mac/core/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.core.mac.core import gap, preamble, crc, padding, last_be
from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
from misoclib.com.liteeth.phy.mii import LiteEthPHYMII


class LiteEthMACCore(Module, AutoCSR):
@@ -80,8 +81,12 @@ def __init__(self, phy, dw, endianness="big",
rx_pipeline += [rx_converter]

# Cross Domain Crossing
tx_cdc = AsyncFIFO(eth_phy_description(dw), 64)
rx_cdc = AsyncFIFO(eth_phy_description(dw), 64)
if isinstance(phy, LiteEthPHYMII):
fifo_depth = 8
else:
fifo_depth = 64
tx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
rx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})

4 changes: 2 additions & 2 deletions misoclib/com/liteeth/core/mac/core/preamble.py
View file
Original file line number Diff line number Diff line change
@@ -47,7 +47,7 @@ def __init__(self, dw):
self.source.last_be.eq(self.sink.last_be)
]
fsm.act("COPY",
Record.connect(self.sink, self.source, leave_out=["data", "last_be"]),
Record.connect(self.sink, self.source, leave_out=set(["data", "last_be"])),
self.source.sop.eq(0),

If(self.sink.stb & self.sink.eop & self.source.ack,
@@ -140,7 +140,7 @@ def __init__(self, dw):
self.source.last_be.eq(self.sink.last_be)
]
fsm.act("COPY",
Record.connect(self.sink, self.source, leave_out=["data", "last_be"]),
Record.connect(self.sink, self.source, leave_out=set(["data", "last_be"])),
self.source.sop.eq(sop),
clr_sop.eq(self.source.stb & self.source.ack),

8 changes: 4 additions & 4 deletions misoclib/mem/litesata/frontend/mirroring.py
View file
Original file line number Diff line number Diff line change
@@ -59,8 +59,8 @@ def __init__(self, n, dw, ctrl):
read_status = Status(read)
self.submodules += read_status
self.comb += [
Record.connect(sink, read, leave_out=["stb", "ack"]),
Record.connect(sink, write, leave_out=["stb", "ack"]),
Record.connect(sink, read, leave_out=set(["stb", "ack"])),
Record.connect(sink, write, leave_out=set(["stb", "ack"])),
read.stb.eq(sink.stb & (sink.read | sink.identify) & ~read_stall),
write.stb.eq(sink.stb & sink.write),
If(sink.read | sink.identify,
@@ -127,8 +127,8 @@ def __init__(self, n, dw, ctrl):
sink_status = Status(sinks[i])
self.submodules += sink_status
self.comb += [
Record.connect(sinks[i], reads[i], leave_out=["stb", "ack"]),
Record.connect(sinks[i], write_striper.sinks[i], leave_out=["stb", "ack"]),
Record.connect(sinks[i], reads[i], leave_out=set(["stb", "ack"])),
Record.connect(sinks[i], write_striper.sinks[i], leave_out=set(["stb", "ack"])),
reads[i].stb.eq(sinks[i].stb & ctrl.reading),
write_striper.sinks[i].stb.eq(sinks[i].stb & ctrl.writing),
sinks[i].ack.eq(reads[i].ack | write_striper.sinks[i].ack),
4 changes: 2 additions & 2 deletions misoclib/mem/litesata/frontend/striping.py
View file
Original file line number Diff line number Diff line change
@@ -39,7 +39,7 @@ def __init__(self, n, dw, mirroring_mode=False):

# split data and ctrl signals (except stb & ack managed in fsm)
for i, s in enumerate(sources):
self.comb += Record.connect(sink, s, leave_out=["stb", "ack", "data"])
self.comb += Record.connect(sink, s, leave_out=set(["stb", "ack", "data"]))
if mirroring_mode:
self.comb += s.data.eq(sink.data)
else:
@@ -82,7 +82,7 @@ def __init__(self, n, dw, mirroring_mode=False):
)

# use first sink for ctrl signals (except for stb, ack & failed)
self.comb += Record.connect(sinks[0], source, leave_out=["stb", "ack", "failed", "data"])
self.comb += Record.connect(sinks[0], source, leave_out=set(["stb", "ack", "failed", "data"]))
# combine datas
if mirroring_mode:
self.comb += source.data.eq(0) # mirroring only used for writes