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Commit 8534562

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committedSep 22, 2015
sim: fix slice assign
1 parent 88f9d72 commit 8534562

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Diff for: ‎migen/sim/core.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -162,13 +162,13 @@ def assign(self, node, value):
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self.assign(element, value & (2**nbits-1))
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value >>= nbits
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elif isinstance(node, _Slice):
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full_value = self.eval(node, True)
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full_value = self.eval(node.value, True)
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# clear bits assigned to by the slice
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full_value &= ~((2**node.stop-1) - (2**node.start-1))
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# set them to the new value
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value &= 2**(node.stop - node.start)-1
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full_value |= value << node.start
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self.assign(node, full_value)
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self.assign(node.value, full_value)
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elif isinstance(node, _ArrayProxy):
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self.assign(node.choices[self.eval(node.key)], value)
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elif isinstance(node, _MemoryLocation):

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