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sbourdeauducqsbourdeauducq
committedSep 24, 2015
interconnect: add bus/bank components from Migen
·
0.120.1
1 parent ecdc410 commit f69674e

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Diff for: ‎misoc/interconnect/__init__.py

Whitespace-only changes.

Diff for: ‎misoc/interconnect/csr.py

+147
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,147 @@
1+
from migen.util.misc import xdir
2+
from migen.fhdl.std import *
3+
from migen.fhdl.tracer import get_obj_var_name
4+
5+
6+
class _CSRBase(HUID):
7+
def __init__(self, size, name):
8+
HUID.__init__(self)
9+
self.name = get_obj_var_name(name)
10+
if self.name is None:
11+
raise ValueError("Cannot extract CSR name from code, need to specify.")
12+
self.size = size
13+
14+
15+
class CSR(_CSRBase):
16+
def __init__(self, size=1, name=None):
17+
_CSRBase.__init__(self, size, name)
18+
self.re = Signal(name=self.name + "_re")
19+
self.r = Signal(self.size, name=self.name + "_r")
20+
self.w = Signal(self.size, name=self.name + "_w")
21+
22+
23+
class _CompoundCSR(_CSRBase, Module):
24+
def __init__(self, size, name):
25+
_CSRBase.__init__(self, size, name)
26+
self.simple_csrs = []
27+
28+
def get_simple_csrs(self):
29+
if not self.finalized:
30+
raise FinalizeError
31+
return self.simple_csrs
32+
33+
def do_finalize(self, busword):
34+
raise NotImplementedError
35+
36+
37+
class CSRStatus(_CompoundCSR):
38+
def __init__(self, size=1, reset=0, name=None):
39+
_CompoundCSR.__init__(self, size, name)
40+
self.status = Signal(self.size, reset=reset)
41+
42+
def do_finalize(self, busword):
43+
nwords = (self.size + busword - 1)//busword
44+
for i in reversed(range(nwords)):
45+
nbits = min(self.size - i*busword, busword)
46+
sc = CSR(nbits, self.name + str(i) if nwords > 1 else self.name)
47+
self.comb += sc.w.eq(self.status[i*busword:i*busword+nbits])
48+
self.simple_csrs.append(sc)
49+
50+
51+
class CSRStorage(_CompoundCSR):
52+
def __init__(self, size=1, reset=0, atomic_write=False, write_from_dev=False, alignment_bits=0, name=None):
53+
_CompoundCSR.__init__(self, size, name)
54+
self.alignment_bits = alignment_bits
55+
self.storage_full = Signal(self.size, reset=reset)
56+
self.storage = Signal(self.size - self.alignment_bits, reset=reset >> alignment_bits)
57+
self.comb += self.storage.eq(self.storage_full[self.alignment_bits:])
58+
self.atomic_write = atomic_write
59+
self.re = Signal()
60+
if write_from_dev:
61+
self.we = Signal()
62+
self.dat_w = Signal(self.size - self.alignment_bits)
63+
self.sync += If(self.we, self.storage_full.eq(self.dat_w << self.alignment_bits))
64+
65+
def do_finalize(self, busword):
66+
nwords = (self.size + busword - 1)//busword
67+
if nwords > 1 and self.atomic_write:
68+
backstore = Signal(self.size - busword, name=self.name + "_backstore")
69+
for i in reversed(range(nwords)):
70+
nbits = min(self.size - i*busword, busword)
71+
sc = CSR(nbits, self.name + str(i) if nwords else self.name)
72+
self.simple_csrs.append(sc)
73+
lo = i*busword
74+
hi = lo+nbits
75+
# read
76+
if lo >= self.alignment_bits:
77+
self.comb += sc.w.eq(self.storage_full[lo:hi])
78+
elif hi > self.alignment_bits:
79+
self.comb += sc.w.eq(Cat(Replicate(0, hi - self.alignment_bits),
80+
self.storage_full[self.alignment_bits:hi]))
81+
else:
82+
self.comb += sc.w.eq(0)
83+
# write
84+
if nwords > 1 and self.atomic_write:
85+
if i:
86+
self.sync += If(sc.re, backstore[lo-busword:hi-busword].eq(sc.r))
87+
else:
88+
self.sync += If(sc.re, self.storage_full.eq(Cat(sc.r, backstore)))
89+
else:
90+
self.sync += If(sc.re, self.storage_full[lo:hi].eq(sc.r))
91+
self.sync += self.re.eq(sc.re)
92+
93+
94+
def csrprefix(prefix, csrs, done):
95+
for csr in csrs:
96+
if csr.huid not in done:
97+
csr.name = prefix + csr.name
98+
done.add(csr.huid)
99+
100+
101+
def memprefix(prefix, memories, done):
102+
for memory in memories:
103+
if memory.huid not in done:
104+
memory.name_override = prefix + memory.name_override
105+
done.add(memory.huid)
106+
107+
108+
def _make_gatherer(method, cls, prefix_cb):
109+
def gatherer(self):
110+
try:
111+
exclude = self.autocsr_exclude
112+
except AttributeError:
113+
exclude = {}
114+
try:
115+
prefixed = self.__prefixed
116+
except AttributeError:
117+
prefixed = self.__prefixed = set()
118+
r = []
119+
for k, v in xdir(self, True):
120+
if k not in exclude:
121+
if isinstance(v, cls):
122+
r.append(v)
123+
elif hasattr(v, method) and callable(getattr(v, method)):
124+
items = getattr(v, method)()
125+
prefix_cb(k + "_", items, prefixed)
126+
r += items
127+
return sorted(r, key=lambda x: x.huid)
128+
return gatherer
129+
130+
131+
class AutoCSR:
132+
get_memories = _make_gatherer("get_memories", Memory, memprefix)
133+
get_csrs = _make_gatherer("get_csrs", _CSRBase, csrprefix)
134+
135+
136+
class GenericBank(Module):
137+
def __init__(self, description, busword):
138+
# Turn description into simple CSRs and claim ownership of compound CSR modules
139+
self.simple_csrs = []
140+
for c in description:
141+
if isinstance(c, CSR):
142+
self.simple_csrs.append(c)
143+
else:
144+
c.finalize(busword)
145+
self.simple_csrs += c.get_simple_csrs()
146+
self.submodules += c
147+
self.decode_bits = bits_for(len(self.simple_csrs)-1)

Diff for: ‎misoc/interconnect/csr_bus.py

+215
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,215 @@
1+
from migen.fhdl.std import *
2+
from migen.bus.transactions import *
3+
from migen.bank.description import CSRStorage
4+
from migen.genlib.record import *
5+
from migen.genlib.misc import chooser
6+
7+
from misoc.interconnect import csr
8+
9+
10+
_layout = [
11+
("adr", "address_width", DIR_M_TO_S),
12+
("we", 1, DIR_M_TO_S),
13+
("dat_w", "data_width", DIR_M_TO_S),
14+
("dat_r", "data_width", DIR_S_TO_M)
15+
]
16+
17+
18+
class Interface(Record):
19+
def __init__(self, data_width=8, address_width=14):
20+
Record.__init__(self, set_layout_parameters(_layout,
21+
data_width=data_width, address_width=address_width))
22+
23+
24+
class Interconnect(Module):
25+
def __init__(self, master, slaves):
26+
self.comb += master.connect(*slaves)
27+
28+
29+
class Initiator(Module):
30+
def __init__(self, generator, bus=None):
31+
self.generator = generator
32+
if bus is None:
33+
bus = Interface()
34+
self.bus = bus
35+
self.transaction = None
36+
self.read_data_ready = False
37+
self.done = False
38+
39+
def do_simulation(self, selfp):
40+
if not self.done:
41+
if self.transaction is not None:
42+
if isinstance(self.transaction, TRead):
43+
if self.read_data_ready:
44+
self.transaction.data = selfp.bus.dat_r
45+
self.transaction = None
46+
self.read_data_ready = False
47+
else:
48+
self.read_data_ready = True
49+
else:
50+
selfp.bus.we = 0
51+
self.transaction = None
52+
if self.transaction is None:
53+
try:
54+
self.transaction = next(self.generator)
55+
except StopIteration:
56+
self.transaction = None
57+
raise StopSimulation
58+
if self.transaction is not None:
59+
selfp.bus.adr = self.transaction.address
60+
if isinstance(self.transaction, TWrite):
61+
selfp.bus.we = 1
62+
selfp.bus.dat_w = self.transaction.data
63+
64+
65+
class SRAM(Module):
66+
def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
67+
if bus is None:
68+
bus = Interface()
69+
self.bus = bus
70+
data_width = flen(self.bus.dat_w)
71+
if isinstance(mem_or_size, Memory):
72+
mem = mem_or_size
73+
else:
74+
mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
75+
csrw_per_memw = (mem.width + data_width - 1)//data_width
76+
word_bits = log2_int(csrw_per_memw)
77+
page_bits = log2_int((mem.depth*csrw_per_memw + 511)//512, False)
78+
if page_bits:
79+
self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
80+
else:
81+
self._page = None
82+
if read_only is None:
83+
if hasattr(mem, "bus_read_only"):
84+
read_only = mem.bus_read_only
85+
else:
86+
read_only = False
87+
88+
###
89+
90+
port = mem.get_port(write_capable=not read_only)
91+
self.specials += mem, port
92+
93+
sel = Signal()
94+
sel_r = Signal()
95+
self.sync += sel_r.eq(sel)
96+
self.comb += sel.eq(self.bus.adr[9:] == address)
97+
98+
if word_bits:
99+
word_index = Signal(word_bits)
100+
word_expanded = Signal(csrw_per_memw*data_width)
101+
self.sync += word_index.eq(self.bus.adr[:word_bits])
102+
self.comb += [
103+
word_expanded.eq(port.dat_r),
104+
If(sel_r,
105+
chooser(word_expanded, word_index, self.bus.dat_r, n=csrw_per_memw, reverse=True)
106+
)
107+
]
108+
if not read_only:
109+
wregs = []
110+
for i in range(csrw_per_memw-1):
111+
wreg = Signal(data_width)
112+
self.sync += If(sel & self.bus.we & (self.bus.adr[:word_bits] == i), wreg.eq(self.bus.dat_w))
113+
wregs.append(wreg)
114+
memword_chunks = [self.bus.dat_w] + list(reversed(wregs))
115+
self.comb += [
116+
port.we.eq(sel & self.bus.we & (self.bus.adr[:word_bits] == csrw_per_memw - 1)),
117+
port.dat_w.eq(Cat(*memword_chunks))
118+
]
119+
else:
120+
self.comb += If(sel_r, self.bus.dat_r.eq(port.dat_r))
121+
if not read_only:
122+
self.comb += [
123+
port.we.eq(sel & self.bus.we),
124+
port.dat_w.eq(self.bus.dat_w)
125+
]
126+
127+
if self._page is None:
128+
self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+flen(port.adr)])
129+
else:
130+
pv = self._page.storage
131+
self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+flen(port.adr)-flen(pv)], pv))
132+
133+
def get_csrs(self):
134+
if self._page is None:
135+
return []
136+
else:
137+
return [self._page]
138+
139+
140+
class CSRBank(csr.GenericBank):
141+
def __init__(self, description, address=0, bus=None):
142+
if bus is None:
143+
bus = Interface()
144+
self.bus = bus
145+
146+
###
147+
148+
GenericBank.__init__(self, description, flen(self.bus.dat_w))
149+
150+
sel = Signal()
151+
self.comb += sel.eq(self.bus.adr[9:] == address)
152+
153+
for i, c in enumerate(self.simple_csrs):
154+
self.comb += [
155+
c.r.eq(self.bus.dat_w[:c.size]),
156+
c.re.eq(sel & \
157+
self.bus.we & \
158+
(self.bus.adr[:self.decode_bits] == i))
159+
]
160+
161+
brcases = dict((i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(self.simple_csrs))
162+
self.sync += [
163+
self.bus.dat_r.eq(0),
164+
If(sel, Case(self.bus.adr[:self.decode_bits], brcases))
165+
]
166+
167+
168+
# address_map(name, memory) returns the CSR offset at which to map
169+
# the CSR object (register bank or memory).
170+
# If memory=None, the object is the register bank of object source.name.
171+
# Otherwise, it is a memory object belonging to source.name.
172+
# address_map is called exactly once for each object at each call to
173+
# scan(), so it can have side effects.
174+
class CSRBankArray(Module):
175+
def __init__(self, source, address_map, *ifargs, **ifkwargs):
176+
self.source = source
177+
self.address_map = address_map
178+
self.scan(ifargs, ifkwargs)
179+
180+
def scan(self, ifargs, ifkwargs):
181+
self.banks = []
182+
self.srams = []
183+
for name, obj in xdir(self.source, True):
184+
if hasattr(obj, "get_csrs"):
185+
csrs = obj.get_csrs()
186+
else:
187+
csrs = []
188+
if hasattr(obj, "get_memories"):
189+
memories = obj.get_memories()
190+
for memory in memories:
191+
mapaddr = self.address_map(name, memory)
192+
if mapaddr is None:
193+
continue
194+
sram_bus = csr.Interface(*ifargs, **ifkwargs)
195+
mmap = csr.SRAM(memory, mapaddr, bus=sram_bus)
196+
self.submodules += mmap
197+
csrs += mmap.get_csrs()
198+
self.srams.append((name, memory, mapaddr, mmap))
199+
if csrs:
200+
mapaddr = self.address_map(name, None)
201+
if mapaddr is None:
202+
continue
203+
bank_bus = csr.Interface(*ifargs, **ifkwargs)
204+
rmap = Bank(csrs, mapaddr, bus=bank_bus)
205+
self.submodules += rmap
206+
self.banks.append((name, csrs, mapaddr, rmap))
207+
208+
def get_rmaps(self):
209+
return [rmap for name, csrs, mapaddr, rmap in self.banks]
210+
211+
def get_mmaps(self):
212+
return [mmap for name, memory, mapaddr, mmap in self.srams]
213+
214+
def get_buses(self):
215+
return [i.bus for i in self.get_rmaps() + self.get_mmaps()]

Diff for: ‎misoc/interconnect/csr_eventmanager.py

+83
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,83 @@
1+
from migen.util.misc import xdir
2+
from migen.fhdl.std import *
3+
from migen.bank.description import *
4+
from migen.genlib.misc import optree
5+
6+
7+
class _EventSource(HUID):
8+
def __init__(self):
9+
HUID.__init__(self)
10+
self.status = Signal() # value in the status register
11+
self.pending = Signal() # value in the pending register + assert irq if unmasked
12+
self.trigger = Signal() # trigger signal interface to the user design
13+
self.clear = Signal() # clearing attempt by W1C to pending register, ignored by some event sources
14+
15+
16+
# set on a positive trigger pulse
17+
class EventSourcePulse(Module, _EventSource):
18+
def __init__(self):
19+
_EventSource.__init__(self)
20+
self.comb += self.status.eq(0)
21+
self.sync += [
22+
If(self.clear, self.pending.eq(0)),
23+
If(self.trigger, self.pending.eq(1))
24+
]
25+
26+
27+
# set on the falling edge of the trigger, status = trigger
28+
class EventSourceProcess(Module, _EventSource):
29+
def __init__(self):
30+
_EventSource.__init__(self)
31+
self.comb += self.status.eq(self.trigger)
32+
old_trigger = Signal()
33+
self.sync += [
34+
If(self.clear, self.pending.eq(0)),
35+
old_trigger.eq(self.trigger),
36+
If(~self.trigger & old_trigger, self.pending.eq(1))
37+
]
38+
39+
40+
# all status set by external trigger
41+
class EventSourceLevel(Module, _EventSource):
42+
def __init__(self):
43+
_EventSource.__init__(self)
44+
self.comb += [
45+
self.status.eq(self.trigger),
46+
self.pending.eq(self.trigger)
47+
]
48+
49+
50+
class EventManager(Module, AutoCSR):
51+
def __init__(self):
52+
self.irq = Signal()
53+
54+
def do_finalize(self):
55+
sources_u = [v for k, v in xdir(self, True) if isinstance(v, _EventSource)]
56+
sources = sorted(sources_u, key=lambda x: x.huid)
57+
n = len(sources)
58+
self.status = CSR(n)
59+
self.pending = CSR(n)
60+
self.enable = CSRStorage(n)
61+
62+
for i, source in enumerate(sources):
63+
self.comb += [
64+
self.status.w[i].eq(source.status),
65+
If(self.pending.re & self.pending.r[i], source.clear.eq(1)),
66+
self.pending.w[i].eq(source.pending)
67+
]
68+
69+
irqs = [self.pending.w[i] & self.enable.storage[i] for i in range(n)]
70+
self.comb += self.irq.eq(optree("|", irqs))
71+
72+
def __setattr__(self, name, value):
73+
object.__setattr__(self, name, value)
74+
if isinstance(value, _EventSource):
75+
if self.finalized:
76+
raise FinalizeError
77+
self.submodules += value
78+
79+
80+
class SharedIRQ(Module):
81+
def __init__(self, *event_managers):
82+
self.irq = Signal()
83+
self.comb += self.irq.eq(optree("|", [ev.irq for ev in event_managers]))

Diff for: ‎misoc/interconnect/lasmibus.py renamed to ‎misoc/interconnect/lasmi_bus.py

File renamed without changes.

Diff for: ‎misoc/interconnect/lasmixbar.py renamed to ‎misoc/interconnect/lasmi_xbar.py

File renamed without changes.

Diff for: ‎misoc/interconnect/wishbone.py

+718
Large diffs are not rendered by default.

Diff for: ‎misoc/interconnect/wishbone2csr.py

+28
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
from migen.fhdl.std import *
2+
from migen.bus import wishbone
3+
from migen.bus import csr
4+
from migen.genlib.misc import timeline
5+
6+
7+
class WB2CSR(Module):
8+
def __init__(self, bus_wishbone=None, bus_csr=None):
9+
if bus_wishbone is None:
10+
bus_wishbone = wishbone.Interface()
11+
self.wishbone = bus_wishbone
12+
if bus_csr is None:
13+
bus_csr = csr.Interface()
14+
self.csr = bus_csr
15+
16+
###
17+
18+
self.sync += [
19+
self.csr.we.eq(0),
20+
self.csr.dat_w.eq(self.wishbone.dat_w),
21+
self.csr.adr.eq(self.wishbone.adr),
22+
self.wishbone.dat_r.eq(self.csr.dat_r)
23+
]
24+
self.sync += timeline(self.wishbone.cyc & self.wishbone.stb, [
25+
(1, [self.csr.we.eq(self.wishbone.we)]),
26+
(2, [self.wishbone.ack.eq(1)]),
27+
(3, [self.wishbone.ack.eq(0)])
28+
])

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