replace flen with len

m-labs · Sep 26, 2015 · 67133f3 · 67133f3
1 parent da425d1
commit 67133f3
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Showing 13 changed files with 44 additions and 44 deletions.
diff --git a/misoc/cores/dfii.py b/misoc/cores/dfii.py
@@ -8,10 +8,10 @@ class PhaseInjector(Module, AutoCSR):
     def __init__(self, phase):
         self._command = CSRStorage(6)  # cs, we, cas, ras, wren, rden
         self._command_issue = CSR()
-        self._address = CSRStorage(flen(phase.address))
-        self._baddress = CSRStorage(flen(phase.bank))
-        self._wrdata = CSRStorage(flen(phase.wrdata))
-        self._rddata = CSRStatus(flen(phase.rddata))
+        self._address = CSRStorage(len(phase.address))
+        self._baddress = CSRStorage(len(phase.bank))
+        self._wrdata = CSRStorage(len(phase.wrdata))
+        self._rddata = CSRStatus(len(phase.rddata))
 
         ###
 

diff --git a/misoc/cores/gpio.py b/misoc/cores/gpio.py
@@ -5,13 +5,13 @@
 
 class GPIOIn(Module, AutoCSR):
     def __init__(self, signal):
-        self._in = CSRStatus(flen(signal))
+        self._in = CSRStatus(len(signal))
         self.specials += MultiReg(signal, self._in.status)
 
 
 class GPIOOut(Module, AutoCSR):
     def __init__(self, signal):
-        self._out = CSRStorage(flen(signal))
+        self._out = CSRStorage(len(signal))
         self.comb += signal.eq(self._out.storage)
 
 

diff --git a/misoc/cores/lasmicon/bankmachine.py b/misoc/cores/lasmicon/bankmachine.py
@@ -35,7 +35,7 @@ def __init__(self, geom_settings, timing_settings, controller_settings, address_
         ###
 
         # Request FIFO
-        self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", flen(req.adr))],
+        self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", len(req.adr))],
                                             controller_settings.req_queue_size)
         self.comb += [
             self.req_fifo.din.we.eq(req.we),

diff --git a/misoc/cores/lasmicon/multiplexer.py b/misoc/cores/lasmicon/multiplexer.py
@@ -34,7 +34,7 @@ def __init__(self, requests):
         self.want_writes = Signal()
         self.want_cmds = Signal()
         # NB: cas_n/ras_n/we_n are 1 when stb is inactive
-        self.cmd = CommandRequestRW(flen(requests[0].a), flen(requests[0].ba))
+        self.cmd = CommandRequestRW(len(requests[0].a), len(requests[0].ba))
 
         ###
 

diff --git a/misoc/cores/liteeth_mini/mac/core/crc.py b/misoc/cores/liteeth_mini/mac/core/crc.py
@@ -138,7 +138,7 @@ def __init__(self, crc_class, description):
 
         # # #
 
-        dw = flen(sink.data)
+        dw = len(sink.data)
         crc = crc_class(dw)
         fsm = FSM(reset_state="IDLE")
         self.submodules += crc, fsm
@@ -219,7 +219,7 @@ def __init__(self, crc_class, description):
 
         # # #
 
-        dw = flen(sink.data)
+        dw = len(sink.data)
         crc = crc_class(dw)
         self.submodules += crc
         ratio = crc.width//dw

diff --git a/misoc/cores/liteeth_mini/phy/__init__.py b/misoc/cores/liteeth_mini/phy/__init__.py
@@ -7,7 +7,7 @@ def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
         # This is a simulation PHY
         from misoc.com.liteethmini.phy.sim import LiteEthPHYSim
         return LiteEthPHYSim(pads)
-    elif hasattr(clock_pads, "gtx") and flen(pads.tx_data) == 8:
+    elif hasattr(clock_pads, "gtx") and len(pads.tx_data) == 8:
         if hasattr(clock_pads, "tx"):
             # This is a 10/100/1G PHY
             from misoc.com.liteethmini.phy.gmii_mii import LiteEthPHYGMIIMII
@@ -19,7 +19,7 @@ def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
     elif hasattr(pads, "rx_ctl"):
         # This is a 10/100/1G RGMII PHY
         raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation")
-    elif flen(pads.tx_data) == 4:
+    elif len(pads.tx_data) == 4:
         # This is a MII PHY
         from misoc.com.liteethmini.phy.mii import LiteEthPHYMII
         return LiteEthPHYMII(clock_pads, pads, **kwargs)

diff --git a/misoc/cores/minicon/test.py b/misoc/cores/minicon/test.py
@@ -32,7 +32,7 @@ def __init__(self, sdrphy, dfi, sdram_geom, sdram_timing, pads, sdram_clk):
         self.submodules.slave = Minicon(phy_settings, sdram_geom, sdram_timing)
 
         self.submodules.tap = wishbone.Tap(self.slave.bus)
-        self.submodules.dc = dc = wishbone.DownConverter(32, phy_settings.nphases*flen(dfi.phases[rdphase].rddata))
+        self.submodules.dc = dc = wishbone.DownConverter(32, phy_settings.nphases*len(dfi.phases[rdphase].rddata))
         self.submodules.master = wishbone.Initiator(self.genxfers(), bus=dc.wishbone_i)
         self.submodules.intercon = wishbone.InterconnectPointToPoint(dc.wishbone_o, self.slave.bus)
 

diff --git a/misoc/cores/sdram_phy/gensdrphy.py b/misoc/cores/sdram_phy/gensdrphy.py
@@ -30,9 +30,9 @@
 
 class GENSDRPHY(Module):
     def __init__(self, pads, module):
-        addressbits = flen(pads.a)
-        bankbits = flen(pads.ba)
-        databits = flen(pads.dq)
+        addressbits = len(pads.a)
+        bankbits = len(pads.ba)
+        databits = len(pads.dq)
 
         self.settings = sdram_settings.PhySettings(
             memtype=module.memtype,

diff --git a/misoc/cores/sdram_phy/k7ddrphy.py b/misoc/cores/sdram_phy/k7ddrphy.py
@@ -9,9 +9,9 @@
 
 class K7DDRPHY(Module, AutoCSR):
     def __init__(self, pads, module):
-        addressbits = flen(pads.a)
-        bankbits = flen(pads.ba)
-        databits = flen(pads.dq)
+        addressbits = len(pads.a)
+        bankbits = len(pads.ba)
+        databits = len(pads.dq)
         nphases = 4
 
         self._wlevel_en = CSRStorage()

diff --git a/misoc/cores/sdram_phy/s6ddrphy.py b/misoc/cores/sdram_phy/s6ddrphy.py
@@ -30,9 +30,9 @@ class S6HalfRateDDRPHY(Module):
     def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
         if module.memtype not in ["DDR", "LPDDR", "DDR2", "DDR3"]:
             raise NotImplementedError("S6HalfRateDDRPHY only supports DDR, LPDDR, DDR2 and DDR3")
-        addressbits = flen(pads.a)
-        bankbits = flen(pads.ba)
-        databits = flen(pads.dq)
+        addressbits = len(pads.a)
+        bankbits = len(pads.ba)
+        databits = len(pads.dq)
         nphases = 2
 
         if module.memtype == "DDR3":
@@ -405,9 +405,9 @@ def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
         half_rate_phy = S6HalfRateDDRPHY(pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment)
         self.submodules += RenameClockDomains(half_rate_phy, {"sys" : "sys2x"})
 
-        addressbits = flen(pads.a)
-        bankbits = flen(pads.ba)
-        databits = flen(pads.dq)
+        addressbits = len(pads.a)
+        bankbits = len(pads.ba)
+        databits = len(pads.dq)
         nphases = 4
 
         self.settings = sdram_settings.PhySettings(

diff --git a/misoc/cores/spi_flash.py b/misoc/cores/spi_flash.py
@@ -35,7 +35,7 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True):
         Optionally supports software bitbanging (for write, erase, or other commands).
         """
         self.bus = bus = wishbone.Interface()
-        spi_width = flen(pads.dq)
+        spi_width = len(pads.dq)
         if with_bitbang:
             self.bitbang = CSRStorage(4)
             self.miso = CSRStatus()
@@ -46,7 +46,7 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True):
         cs_n = Signal(reset=1)
         clk = Signal()
         dq_oe = Signal()
-        wbone_width = flen(bus.dat_r)
+        wbone_width = len(bus.dat_r)
 
 
         read_cmd_params = {

diff --git a/misoc/interconnect/csr_bus.py b/misoc/interconnect/csr_bus.py
@@ -31,7 +31,7 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
         if bus is None:
             bus = Interface()
         self.bus = bus
-        data_width = flen(self.bus.dat_w)
+        data_width = len(self.bus.dat_w)
         if isinstance(mem_or_size, Memory):
             mem = mem_or_size
         else:
@@ -89,10 +89,10 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
                 ]
 
         if self._page is None:
-            self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+flen(port.adr)])
+            self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+len(port.adr)])
         else:
             pv = self._page.storage
-            self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+flen(port.adr)-flen(pv)], pv))
+            self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+len(port.adr)-len(pv)], pv))
 
     def get_csrs(self):
         if self._page is None:
@@ -109,7 +109,7 @@ def __init__(self, description, address=0, bus=None):
 
         ###
 
-        csr.GenericBank.__init__(self, description, flen(self.bus.dat_w))
+        csr.GenericBank.__init__(self, description, len(self.bus.dat_w))
 
         sel = Signal()
         self.comb += sel.eq(self.bus.adr[9:] == address)

diff --git a/misoc/interconnect/wishbone.py b/misoc/interconnect/wishbone.py
@@ -102,7 +102,7 @@ def __init__(self, master, slaves, register=False):
         ]
 
         # mux (1-hot) slave data return
-        masked = [Replicate(slave_sel_r[i], flen(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
+        masked = [Replicate(slave_sel_r[i], len(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
         self.comb += master.dat_r.eq(reduce(or_, masked))
 
 
@@ -144,8 +144,8 @@ class DownConverter(Module):
         Manage err signal? (Not implemented since we generally don't use it on Migen/MiSoC modules)
     """
     def __init__(self, master, slave):
-        dw_from = flen(master.dat_r)
-        dw_to = flen(slave.dat_w)
+        dw_from = len(master.dat_r)
+        dw_to = len(slave.dat_w)
         ratio = dw_from//dw_to
 
         # # #
@@ -251,8 +251,8 @@ class UpConverter(Module):
         Manage err signal? (Not implemented since we generally don't use it on Migen/MiSoC modules)
     """
     def __init__(self, master, slave):
-        dw_from = flen(master.dat_r)
-        dw_to = flen(slave.dat_w)
+        dw_from = len(master.dat_r)
+        dw_to = len(slave.dat_w)
         ratio = dw_to//dw_from
         ratiobits = log2_int(ratio)
 
@@ -402,8 +402,8 @@ def __init__(self, master, slave):
 
         # # #
 
-        dw_from = flen(master.dat_r)
-        dw_to = flen(slave.dat_r)
+        dw_from = len(master.dat_r)
+        dw_to = len(slave.dat_r)
         if dw_from > dw_to:
             downconverter = DownConverter(master, slave)
             self.submodules += downconverter
@@ -426,8 +426,8 @@ def __init__(self, cachesize, master, slave):
 
         ###
 
-        dw_from = flen(master.dat_r)
-        dw_to = flen(slave.dat_r)
+        dw_from = len(master.dat_r)
+        dw_to = len(slave.dat_r)
         if dw_to > dw_from and (dw_to % dw_from) != 0:
             raise ValueError("Slave data width must be a multiple of {dw}".format(dw=dw_from))
         if dw_to < dw_from and (dw_from % dw_to) != 0:
@@ -436,7 +436,7 @@ def __init__(self, cachesize, master, slave):
         # Split address:
         # TAG | LINE NUMBER | LINE OFFSET
         offsetbits = log2_int(max(dw_to//dw_from, 1))
-        addressbits = flen(slave.adr) + offsetbits
+        addressbits = len(slave.adr) + offsetbits
         linebits = log2_int(cachesize) - offsetbits
         tagbits = addressbits - linebits
         wordbits = log2_int(max(dw_from//dw_to, 1))
@@ -574,7 +574,7 @@ def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
         if bus is None:
             bus = Interface()
         self.bus = bus
-        bus_data_width = flen(self.bus.dat_r)
+        bus_data_width = len(self.bus.dat_r)
         if isinstance(mem_or_size, Memory):
             assert(mem_or_size.width <= bus_data_width)
             self.mem = mem_or_size
@@ -597,7 +597,7 @@ def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
                 for i in range(4)]
         # address and data
         self.comb += [
-            port.adr.eq(self.bus.adr[:flen(port.adr)]),
+            port.adr.eq(self.bus.adr[:len(port.adr)]),
             self.bus.dat_r.eq(port.dat_r)
         ]
         if not read_only:
@@ -617,7 +617,7 @@ def __init__(self, description, bus=None):
 
         ###
 
-        GenericBank.__init__(self, description, flen(self.bus.dat_w))
+        GenericBank.__init__(self, description, len(self.bus.dat_w))
 
         for i, c in enumerate(self.simple_csrs):
             self.comb += [