Skip to content

Commit 67133f3

Browse files
sbourdeauducqsbourdeauducq
committedSep 26, 2015
replace flen with len
·
0.120.1
1 parent da425d1 commit 67133f3

File tree

13 files changed

+44
-44
lines changed

13 files changed

+44
-44
lines changed
 

Diff for: ‎misoc/cores/dfii.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,10 @@ class PhaseInjector(Module, AutoCSR):
88
def __init__(self, phase):
99
self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
1010
self._command_issue = CSR()
11-
self._address = CSRStorage(flen(phase.address))
12-
self._baddress = CSRStorage(flen(phase.bank))
13-
self._wrdata = CSRStorage(flen(phase.wrdata))
14-
self._rddata = CSRStatus(flen(phase.rddata))
11+
self._address = CSRStorage(len(phase.address))
12+
self._baddress = CSRStorage(len(phase.bank))
13+
self._wrdata = CSRStorage(len(phase.wrdata))
14+
self._rddata = CSRStatus(len(phase.rddata))
1515

1616
###
1717

Diff for: ‎misoc/cores/gpio.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -5,13 +5,13 @@
55

66
class GPIOIn(Module, AutoCSR):
77
def __init__(self, signal):
8-
self._in = CSRStatus(flen(signal))
8+
self._in = CSRStatus(len(signal))
99
self.specials += MultiReg(signal, self._in.status)
1010

1111

1212
class GPIOOut(Module, AutoCSR):
1313
def __init__(self, signal):
14-
self._out = CSRStorage(flen(signal))
14+
self._out = CSRStorage(len(signal))
1515
self.comb += signal.eq(self._out.storage)
1616

1717

Diff for: ‎misoc/cores/lasmicon/bankmachine.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ def __init__(self, geom_settings, timing_settings, controller_settings, address_
3535
###
3636

3737
# Request FIFO
38-
self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", flen(req.adr))],
38+
self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", len(req.adr))],
3939
controller_settings.req_queue_size)
4040
self.comb += [
4141
self.req_fifo.din.we.eq(req.we),

Diff for: ‎misoc/cores/lasmicon/multiplexer.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ def __init__(self, requests):
3434
self.want_writes = Signal()
3535
self.want_cmds = Signal()
3636
# NB: cas_n/ras_n/we_n are 1 when stb is inactive
37-
self.cmd = CommandRequestRW(flen(requests[0].a), flen(requests[0].ba))
37+
self.cmd = CommandRequestRW(len(requests[0].a), len(requests[0].ba))
3838

3939
###
4040

Diff for: ‎misoc/cores/liteeth_mini/mac/core/crc.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,7 @@ def __init__(self, crc_class, description):
138138

139139
# # #
140140

141-
dw = flen(sink.data)
141+
dw = len(sink.data)
142142
crc = crc_class(dw)
143143
fsm = FSM(reset_state="IDLE")
144144
self.submodules += crc, fsm
@@ -219,7 +219,7 @@ def __init__(self, crc_class, description):
219219

220220
# # #
221221

222-
dw = flen(sink.data)
222+
dw = len(sink.data)
223223
crc = crc_class(dw)
224224
self.submodules += crc
225225
ratio = crc.width//dw

Diff for: ‎misoc/cores/liteeth_mini/phy/__init__.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
77
# This is a simulation PHY
88
from misoc.com.liteethmini.phy.sim import LiteEthPHYSim
99
return LiteEthPHYSim(pads)
10-
elif hasattr(clock_pads, "gtx") and flen(pads.tx_data) == 8:
10+
elif hasattr(clock_pads, "gtx") and len(pads.tx_data) == 8:
1111
if hasattr(clock_pads, "tx"):
1212
# This is a 10/100/1G PHY
1313
from misoc.com.liteethmini.phy.gmii_mii import LiteEthPHYGMIIMII
@@ -19,7 +19,7 @@ def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
1919
elif hasattr(pads, "rx_ctl"):
2020
# This is a 10/100/1G RGMII PHY
2121
raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation")
22-
elif flen(pads.tx_data) == 4:
22+
elif len(pads.tx_data) == 4:
2323
# This is a MII PHY
2424
from misoc.com.liteethmini.phy.mii import LiteEthPHYMII
2525
return LiteEthPHYMII(clock_pads, pads, **kwargs)

Diff for: ‎misoc/cores/minicon/test.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ def __init__(self, sdrphy, dfi, sdram_geom, sdram_timing, pads, sdram_clk):
3232
self.submodules.slave = Minicon(phy_settings, sdram_geom, sdram_timing)
3333

3434
self.submodules.tap = wishbone.Tap(self.slave.bus)
35-
self.submodules.dc = dc = wishbone.DownConverter(32, phy_settings.nphases*flen(dfi.phases[rdphase].rddata))
35+
self.submodules.dc = dc = wishbone.DownConverter(32, phy_settings.nphases*len(dfi.phases[rdphase].rddata))
3636
self.submodules.master = wishbone.Initiator(self.genxfers(), bus=dc.wishbone_i)
3737
self.submodules.intercon = wishbone.InterconnectPointToPoint(dc.wishbone_o, self.slave.bus)
3838

Diff for: ‎misoc/cores/sdram_phy/gensdrphy.py

+3-3
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,9 @@
3030

3131
class GENSDRPHY(Module):
3232
def __init__(self, pads, module):
33-
addressbits = flen(pads.a)
34-
bankbits = flen(pads.ba)
35-
databits = flen(pads.dq)
33+
addressbits = len(pads.a)
34+
bankbits = len(pads.ba)
35+
databits = len(pads.dq)
3636

3737
self.settings = sdram_settings.PhySettings(
3838
memtype=module.memtype,

Diff for: ‎misoc/cores/sdram_phy/k7ddrphy.py

+3-3
Original file line numberDiff line numberDiff line change
@@ -9,9 +9,9 @@
99

1010
class K7DDRPHY(Module, AutoCSR):
1111
def __init__(self, pads, module):
12-
addressbits = flen(pads.a)
13-
bankbits = flen(pads.ba)
14-
databits = flen(pads.dq)
12+
addressbits = len(pads.a)
13+
bankbits = len(pads.ba)
14+
databits = len(pads.dq)
1515
nphases = 4
1616

1717
self._wlevel_en = CSRStorage()

Diff for: ‎misoc/cores/sdram_phy/s6ddrphy.py

+6-6
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,9 @@ class S6HalfRateDDRPHY(Module):
3030
def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
3131
if module.memtype not in ["DDR", "LPDDR", "DDR2", "DDR3"]:
3232
raise NotImplementedError("S6HalfRateDDRPHY only supports DDR, LPDDR, DDR2 and DDR3")
33-
addressbits = flen(pads.a)
34-
bankbits = flen(pads.ba)
35-
databits = flen(pads.dq)
33+
addressbits = len(pads.a)
34+
bankbits = len(pads.ba)
35+
databits = len(pads.dq)
3636
nphases = 2
3737

3838
if module.memtype == "DDR3":
@@ -405,9 +405,9 @@ def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
405405
half_rate_phy = S6HalfRateDDRPHY(pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment)
406406
self.submodules += RenameClockDomains(half_rate_phy, {"sys" : "sys2x"})
407407

408-
addressbits = flen(pads.a)
409-
bankbits = flen(pads.ba)
410-
databits = flen(pads.dq)
408+
addressbits = len(pads.a)
409+
bankbits = len(pads.ba)
410+
databits = len(pads.dq)
411411
nphases = 4
412412

413413
self.settings = sdram_settings.PhySettings(

Diff for: ‎misoc/cores/spi_flash.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True):
3535
Optionally supports software bitbanging (for write, erase, or other commands).
3636
"""
3737
self.bus = bus = wishbone.Interface()
38-
spi_width = flen(pads.dq)
38+
spi_width = len(pads.dq)
3939
if with_bitbang:
4040
self.bitbang = CSRStorage(4)
4141
self.miso = CSRStatus()
@@ -46,7 +46,7 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True):
4646
cs_n = Signal(reset=1)
4747
clk = Signal()
4848
dq_oe = Signal()
49-
wbone_width = flen(bus.dat_r)
49+
wbone_width = len(bus.dat_r)
5050

5151

5252
read_cmd_params = {

Diff for: ‎misoc/interconnect/csr_bus.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
3131
if bus is None:
3232
bus = Interface()
3333
self.bus = bus
34-
data_width = flen(self.bus.dat_w)
34+
data_width = len(self.bus.dat_w)
3535
if isinstance(mem_or_size, Memory):
3636
mem = mem_or_size
3737
else:
@@ -89,10 +89,10 @@ def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
8989
]
9090

9191
if self._page is None:
92-
self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+flen(port.adr)])
92+
self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+len(port.adr)])
9393
else:
9494
pv = self._page.storage
95-
self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+flen(port.adr)-flen(pv)], pv))
95+
self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+len(port.adr)-len(pv)], pv))
9696

9797
def get_csrs(self):
9898
if self._page is None:
@@ -109,7 +109,7 @@ def __init__(self, description, address=0, bus=None):
109109

110110
###
111111

112-
csr.GenericBank.__init__(self, description, flen(self.bus.dat_w))
112+
csr.GenericBank.__init__(self, description, len(self.bus.dat_w))
113113

114114
sel = Signal()
115115
self.comb += sel.eq(self.bus.adr[9:] == address)

Diff for: ‎misoc/interconnect/wishbone.py

+13-13
Original file line numberDiff line numberDiff line change
@@ -102,7 +102,7 @@ def __init__(self, master, slaves, register=False):
102102
]
103103

104104
# mux (1-hot) slave data return
105-
masked = [Replicate(slave_sel_r[i], flen(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
105+
masked = [Replicate(slave_sel_r[i], len(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
106106
self.comb += master.dat_r.eq(reduce(or_, masked))
107107

108108

@@ -144,8 +144,8 @@ class DownConverter(Module):
144144
Manage err signal? (Not implemented since we generally don't use it on Migen/MiSoC modules)
145145
"""
146146
def __init__(self, master, slave):
147-
dw_from = flen(master.dat_r)
148-
dw_to = flen(slave.dat_w)
147+
dw_from = len(master.dat_r)
148+
dw_to = len(slave.dat_w)
149149
ratio = dw_from//dw_to
150150

151151
# # #
@@ -251,8 +251,8 @@ class UpConverter(Module):
251251
Manage err signal? (Not implemented since we generally don't use it on Migen/MiSoC modules)
252252
"""
253253
def __init__(self, master, slave):
254-
dw_from = flen(master.dat_r)
255-
dw_to = flen(slave.dat_w)
254+
dw_from = len(master.dat_r)
255+
dw_to = len(slave.dat_w)
256256
ratio = dw_to//dw_from
257257
ratiobits = log2_int(ratio)
258258

@@ -402,8 +402,8 @@ def __init__(self, master, slave):
402402

403403
# # #
404404

405-
dw_from = flen(master.dat_r)
406-
dw_to = flen(slave.dat_r)
405+
dw_from = len(master.dat_r)
406+
dw_to = len(slave.dat_r)
407407
if dw_from > dw_to:
408408
downconverter = DownConverter(master, slave)
409409
self.submodules += downconverter
@@ -426,8 +426,8 @@ def __init__(self, cachesize, master, slave):
426426

427427
###
428428

429-
dw_from = flen(master.dat_r)
430-
dw_to = flen(slave.dat_r)
429+
dw_from = len(master.dat_r)
430+
dw_to = len(slave.dat_r)
431431
if dw_to > dw_from and (dw_to % dw_from) != 0:
432432
raise ValueError("Slave data width must be a multiple of {dw}".format(dw=dw_from))
433433
if dw_to < dw_from and (dw_from % dw_to) != 0:
@@ -436,7 +436,7 @@ def __init__(self, cachesize, master, slave):
436436
# Split address:
437437
# TAG | LINE NUMBER | LINE OFFSET
438438
offsetbits = log2_int(max(dw_to//dw_from, 1))
439-
addressbits = flen(slave.adr) + offsetbits
439+
addressbits = len(slave.adr) + offsetbits
440440
linebits = log2_int(cachesize) - offsetbits
441441
tagbits = addressbits - linebits
442442
wordbits = log2_int(max(dw_from//dw_to, 1))
@@ -574,7 +574,7 @@ def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
574574
if bus is None:
575575
bus = Interface()
576576
self.bus = bus
577-
bus_data_width = flen(self.bus.dat_r)
577+
bus_data_width = len(self.bus.dat_r)
578578
if isinstance(mem_or_size, Memory):
579579
assert(mem_or_size.width <= bus_data_width)
580580
self.mem = mem_or_size
@@ -597,7 +597,7 @@ def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
597597
for i in range(4)]
598598
# address and data
599599
self.comb += [
600-
port.adr.eq(self.bus.adr[:flen(port.adr)]),
600+
port.adr.eq(self.bus.adr[:len(port.adr)]),
601601
self.bus.dat_r.eq(port.dat_r)
602602
]
603603
if not read_only:
@@ -617,7 +617,7 @@ def __init__(self, description, bus=None):
617617

618618
###
619619

620-
GenericBank.__init__(self, description, flen(self.bus.dat_w))
620+
GenericBank.__init__(self, description, len(self.bus.dat_w))
621621

622622
for i, c in enumerate(self.simple_csrs):
623623
self.comb += [

0 commit comments

Comments
 (0)
Please sign in to comment.