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sbourdeauducqsbourdeauducq
committedSep 26, 2015
fhdl: replace flen with len
·
0.9.20.2
1 parent fa1e8cd commit 808cf06

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13 files changed

+63
-72
lines changed

13 files changed

+63
-72
lines changed
 

Diff for: ‎examples/basic/graycounter.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ def tb(dut):
88
prng = Random(7345)
99
for i in range(35):
1010
print("{0:0{1}b} CE={2} bin={3}".format((yield dut.q),
11-
flen(dut.q), (yield dut.ce), (yield dut.q_binary)))
11+
len(dut.q), (yield dut.ce), (yield dut.q_binary)))
1212
yield dut.ce.eq(prng.getrandbits(1))
1313
yield
1414

Diff for: ‎migen/build/platforms/usrp_b100.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,7 @@ def do_finalize(self, fragment):
135135
(gpif.ctl, "in"), (gpif.adr, "out"),
136136
(gpif.slwr, "out"), (gpif.sloe, "out"),
137137
(gpif.slrd, "out"), (gpif.pktend, "out")]:
138-
if flen(i) > 1:
138+
if len(i) > 1:
139139
q = "(*)"
140140
else:
141141
q = ""

Diff for: ‎migen/fhdl/bitcontainer.py

+20-24
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
from migen.fhdl import structure as f
22

33

4-
__all__ = ["log2_int", "bits_for", "flen"]
4+
__all__ = ["log2_int", "bits_for", "value_bits_sign"]
55

66

77
def log2_int(n, need_pow2=True):
@@ -27,6 +27,25 @@ def bits_for(n, require_sign_bit=False):
2727

2828

2929
def value_bits_sign(v):
30+
"""Bit length and signedness of a value.
31+
32+
Parameters
33+
----------
34+
v : Value
35+
36+
Returns
37+
-------
38+
int, bool
39+
Number of bits required to store `v` or available in `v`, followed by
40+
whether `v` has a sign bit (included in the bit count).
41+
42+
Examples
43+
--------
44+
>>> value_bits_sign(f.Signal(8))
45+
8, False
46+
>>> value_bits_sign(C(0xaa))
47+
8, False
48+
"""
3049
if isinstance(v, (f.Constant, f.Signal)):
3150
return v.nbits, v.signed
3251
elif isinstance(v, (f.ClockSignal, f.ResetSignal)):
@@ -100,26 +119,3 @@ def value_bits_sign(v):
100119
else:
101120
raise TypeError("Can not calculate bit length of {} {}".format(
102121
type(v), v))
103-
104-
105-
def flen(v):
106-
"""Bit length of an expression
107-
108-
Parameters
109-
----------
110-
v : int, bool or Value
111-
112-
Returns
113-
-------
114-
int
115-
Number of bits required to store `v` or available in `v`
116-
117-
Examples
118-
--------
119-
>>> flen(f.Signal(8))
120-
8
121-
>>> flen(0xaa)
122-
8
123-
"""
124-
return value_bits_sign(v)[0]
125-

Diff for: ‎migen/fhdl/structure.py

+7-6
Original file line numberDiff line numberDiff line change
@@ -89,11 +89,12 @@ def __gt__(self, other):
8989
def __ge__(self, other):
9090
return _Operator(">=", [self, other])
9191

92+
def __len__(self):
93+
from migen.fhdl.bitcontainer import value_bits_sign
94+
return value_bits_sign(self)[0]
9295

9396
def __getitem__(self, key):
94-
from migen.fhdl.bitcontainer import flen
95-
96-
n = flen(self)
97+
n = len(self)
9798
if isinstance(key, int):
9899
if key >= n:
99100
raise IndexError
@@ -187,7 +188,7 @@ class Cat(_Value):
187188
meeting these properties. The bit length of the return value is the sum of
188189
the bit lengths of the arguments::
189190
190-
flen(Cat(args)) == sum(flen(arg) for arg in args)
191+
len(Cat(args)) == sum(len(arg) for arg in args)
191192
192193
Parameters
193194
----------
@@ -210,7 +211,7 @@ class Replicate(_Value):
210211
An input value is replicated (repeated) several times
211212
to be used on the RHS of assignments::
212213
213-
flen(Replicate(s, n)) == flen(s)*n
214+
len(Replicate(s, n)) == len(s)*n
214215
215216
Parameters
216217
----------
@@ -356,7 +357,7 @@ def like(cls, other, **kwargs):
356357
other : _Value
357358
Object to base this Signal on.
358359
359-
See `migen.fhdl.bitcontainer.value_bits_sign`() for details.
360+
See `migen.fhdl.bitcontainer.value_bits_sign` for details.
360361
"""
361362
from migen.fhdl.bitcontainer import value_bits_sign
362363
return cls(bits_sign=value_bits_sign(other), **kwargs)

Diff for: ‎migen/fhdl/verilog.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
from migen.fhdl.structure import *
55
from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
66
from migen.fhdl.tools import *
7-
from migen.fhdl.bitcontainer import bits_for, flen
7+
from migen.fhdl.bitcontainer import bits_for
88
from migen.fhdl.namer import build_namespace
99
from migen.fhdl.conv_output import ConvOutput
1010

@@ -36,8 +36,8 @@ def _printsig(ns, s):
3636
n = "signed "
3737
else:
3838
n = ""
39-
if flen(s) > 1:
40-
n += "[" + str(flen(s)-1) + ":0] "
39+
if len(s) > 1:
40+
n += "[" + str(len(s)-1) + ":0] "
4141
n += ns.get_name(s)
4242
return n
4343

@@ -93,7 +93,7 @@ def _printexpr(ns, node):
9393
elif isinstance(node, _Slice):
9494
# Verilog does not like us slicing non-array signals...
9595
if isinstance(node.value, Signal) \
96-
and flen(node.value) == 1 \
96+
and len(node.value) == 1 \
9797
and node.start == 0 and node.stop == 1:
9898
return _printexpr(ns, node.value)
9999

Diff for: ‎migen/genlib/fifo.py

+1-2
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,12 @@
11
from migen.fhdl.structure import *
22
from migen.fhdl.module import Module
33
from migen.fhdl.specials import Memory
4-
from migen.fhdl.bitcontainer import flen
54
from migen.genlib.cdc import NoRetiming, MultiReg, GrayCounter
65
from migen.genlib.record import layout_len, Record
76

87

98
def _inc(signal, modulo):
10-
if modulo == 2**flen(signal):
9+
if modulo == 2**len(signal):
1110
return signal.eq(signal + 1)
1211
else:
1312
return If(signal == (modulo - 1),

Diff for: ‎migen/genlib/misc.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -19,8 +19,8 @@ def displacer(signal, shift, output, n=None, reverse=False):
1919
if shift is None:
2020
return output.eq(signal)
2121
if n is None:
22-
n = 2**flen(shift)
23-
w = flen(signal)
22+
n = 2**len(shift)
23+
w = len(signal)
2424
if reverse:
2525
r = reversed(range(n))
2626
else:
@@ -33,8 +33,8 @@ def chooser(signal, shift, output, n=None, reverse=False):
3333
if shift is None:
3434
return output.eq(signal)
3535
if n is None:
36-
n = 2**flen(shift)
37-
w = flen(output)
36+
n = 2**len(shift)
37+
w = len(output)
3838
cases = {}
3939
for i in range(n):
4040
if reverse:

Diff for: ‎migen/sim/core.py

+2-3
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,6 @@
44
from migen.fhdl.structure import (_Value, _Statement,
55
_Operator, _Slice, _ArrayProxy,
66
_Assign, _Fragment)
7-
from migen.fhdl.bitcontainer import flen
87
from migen.fhdl.tools import list_signals, list_targets, insert_resets
98
from migen.fhdl.simplify import MemoryToArray
109
from migen.fhdl.specials import _MemoryLocation
@@ -123,7 +122,7 @@ def eval(self, node, postcommit=False):
123122
shift = 0
124123
r = 0
125124
for element in node.l:
126-
nbits = flen(element)
125+
nbits = len(element)
127126
# make value always positive
128127
r |= (self.eval(element, postcommit) & (2**nbits-1)) << shift
129128
shift += nbits
@@ -158,7 +157,7 @@ def assign(self, node, value):
158157
self.modifications[node] = value
159158
elif isinstance(node, Cat):
160159
for element in node.l:
161-
nbits = flen(element)
160+
nbits = len(element)
162161
self.assign(element, value & (2**nbits-1))
163162
value >>= nbits
164163
elif isinstance(node, _Slice):

Diff for: ‎migen/sim/vcd.py

+2-3
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
11
from itertools import count
22

3-
from migen.fhdl.bitcontainer import flen
43
from migen.fhdl.namer import build_namespace
54

65

@@ -30,7 +29,7 @@ def __init__(self, filename, signals):
3029
code = next(codes)
3130
self.codes[signal] = code
3231
self.fo.write("$var wire {len} {code} {name} $end\n"
33-
.format(name=name, code=code, len=flen(signal)))
32+
.format(name=name, code=code, len=len(signal)))
3433
self.fo.write("$dumpvars\n")
3534
for signal in signals:
3635
value = signal.reset.value
@@ -43,7 +42,7 @@ def __init__(self, filename, signals):
4342
raise
4443

4544
def _write_value(self, signal, value):
46-
l = flen(signal)
45+
l = len(signal)
4746
if value < 0:
4847
value += 2**l
4948
if l > 1:

Diff for: ‎migen/test/test_coding.py

+12-12
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,9 @@ def __init__(self):
1212
self.submodules.dut = Encoder(8)
1313

1414
def test_sizes(self):
15-
self.assertEqual(flen(self.tb.dut.i), 8)
16-
self.assertEqual(flen(self.tb.dut.o), 3)
17-
self.assertEqual(flen(self.tb.dut.n), 1)
15+
self.assertEqual(len(self.tb.dut.i), 8)
16+
self.assertEqual(len(self.tb.dut.o), 3)
17+
self.assertEqual(len(self.tb.dut.n), 1)
1818

1919
def test_run_sequence(self):
2020
seq = list(range(1<<8))
@@ -36,9 +36,9 @@ def __init__(self):
3636
self.submodules.dut = PriorityEncoder(8)
3737

3838
def test_sizes(self):
39-
self.assertEqual(flen(self.tb.dut.i), 8)
40-
self.assertEqual(flen(self.tb.dut.o), 3)
41-
self.assertEqual(flen(self.tb.dut.n), 1)
39+
self.assertEqual(len(self.tb.dut.i), 8)
40+
self.assertEqual(len(self.tb.dut.o), 3)
41+
self.assertEqual(len(self.tb.dut.n), 1)
4242

4343
def test_run_sequence(self):
4444
seq = list(range(1<<8))
@@ -64,9 +64,9 @@ def __init__(self):
6464
self.submodules.dut = Decoder(8)
6565

6666
def test_sizes(self):
67-
self.assertEqual(flen(self.tb.dut.i), 3)
68-
self.assertEqual(flen(self.tb.dut.o), 8)
69-
self.assertEqual(flen(self.tb.dut.n), 1)
67+
self.assertEqual(len(self.tb.dut.i), 3)
68+
self.assertEqual(len(self.tb.dut.o), 8)
69+
self.assertEqual(len(self.tb.dut.n), 1)
7070

7171
def test_run_sequence(self):
7272
seq = list(range(8*2))
@@ -91,9 +91,9 @@ def __init__(self):
9191
self.submodules.dut = PriorityEncoder(1)
9292

9393
def test_sizes(self):
94-
self.assertEqual(flen(self.tb.dut.i), 1)
95-
self.assertEqual(flen(self.tb.dut.o), 1)
96-
self.assertEqual(flen(self.tb.dut.n), 1)
94+
self.assertEqual(len(self.tb.dut.i), 1)
95+
self.assertEqual(len(self.tb.dut.o), 1)
96+
self.assertEqual(len(self.tb.dut.n), 1)
9797

9898
def test_run_sequence(self):
9999
seq = list(range(1))

Diff for: ‎migen/test/test_fifo.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,8 @@ def __init__(self):
2020
]
2121

2222
def test_sizes(self):
23-
self.assertEqual(flen(self.tb.dut.din_bits), 64)
24-
self.assertEqual(flen(self.tb.dut.dout_bits), 64)
23+
self.assertEqual(len(self.tb.dut.din_bits), 64)
24+
self.assertEqual(len(self.tb.dut.dout_bits), 64)
2525

2626
def test_run_sequence(self):
2727
seq = list(range(20))

Diff for: ‎migen/test/test_size.py

+4-7
Original file line numberDiff line numberDiff line change
@@ -13,10 +13,7 @@ def setUp(self):
1313
self.j = C(-127)
1414
self.s = Signal((13, True))
1515

16-
def test_flen(self):
17-
self.assertEqual(flen(self.s), 13)
18-
self.assertEqual(flen(self.i), 8)
19-
self.assertEqual(flen(self.j), 8)
20-
21-
def test_flen_type(self):
22-
self.assertRaises(TypeError, flen, [])
16+
def test_len(self):
17+
self.assertEqual(len(self.s), 13)
18+
self.assertEqual(len(self.i), 8)
19+
self.assertEqual(len(self.j), 8)

Diff for: ‎migen/test/test_sort.py

+3-3
Original file line numberDiff line numberDiff line change
@@ -16,14 +16,14 @@ def test_sizes(self):
1616
self.assertEqual(len(self.tb.dut.i), 8)
1717
self.assertEqual(len(self.tb.dut.o), 8)
1818
for i in range(8):
19-
self.assertEqual(flen(self.tb.dut.i[i]), 4)
20-
self.assertEqual(flen(self.tb.dut.o[i]), 4)
19+
self.assertEqual(len(self.tb.dut.i[i]), 4)
20+
self.assertEqual(len(self.tb.dut.o[i]), 4)
2121

2222
def test_sort(self):
2323
def gen():
2424
for repeat in range(20):
2525
for i in self.tb.dut.i:
26-
yield i.eq(randrange(1<<flen(i)))
26+
yield i.eq(randrange(1<<len(i)))
2727
yield
2828
self.assertEqual(sorted((yield self.tb.dut.i)),
2929
(yield self.tb.dut.o))

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