fhdl: replace flen with len

m-labs · Sep 26, 2015 · 808cf06 · 808cf06
1 parent fa1e8cd
commit 808cf06
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Showing 13 changed files with 63 additions and 72 deletions.
diff --git a/examples/basic/graycounter.py b/examples/basic/graycounter.py
@@ -8,7 +8,7 @@ def tb(dut):
     prng = Random(7345)
     for i in range(35):
         print("{0:0{1}b} CE={2} bin={3}".format((yield dut.q),
-            flen(dut.q), (yield dut.ce), (yield dut.q_binary)))
+            len(dut.q), (yield dut.ce), (yield dut.q_binary)))
         yield dut.ce.eq(prng.getrandbits(1))
         yield
 

diff --git a/migen/build/platforms/usrp_b100.py b/migen/build/platforms/usrp_b100.py
@@ -135,7 +135,7 @@ def do_finalize(self, fragment):
                     (gpif.ctl, "in"), (gpif.adr, "out"),
                     (gpif.slwr, "out"), (gpif.sloe, "out"),
                     (gpif.slrd, "out"), (gpif.pktend, "out")]:
-                if flen(i) > 1:
+                if len(i) > 1:
                     q = "(*)"
                 else:
                     q = ""

diff --git a/migen/fhdl/bitcontainer.py b/migen/fhdl/bitcontainer.py
@@ -1,7 +1,7 @@
 from migen.fhdl import structure as f
 
 
-__all__ = ["log2_int", "bits_for", "flen"]
+__all__ = ["log2_int", "bits_for", "value_bits_sign"]
 
 
 def log2_int(n, need_pow2=True):
@@ -27,6 +27,25 @@ def bits_for(n, require_sign_bit=False):
 
 
 def value_bits_sign(v):
+    """Bit length and signedness of a value.
+
+    Parameters
+    ----------
+    v : Value
+
+    Returns
+    -------
+    int, bool
+        Number of bits required to store `v` or available in `v`, followed by
+        whether `v` has a sign bit (included in the bit count).
+
+    Examples
+    --------
+    >>> value_bits_sign(f.Signal(8))
+    8, False
+    >>> value_bits_sign(C(0xaa))
+    8, False
+    """
     if isinstance(v, (f.Constant, f.Signal)):
         return v.nbits, v.signed
     elif isinstance(v, (f.ClockSignal, f.ResetSignal)):
@@ -100,26 +119,3 @@ def value_bits_sign(v):
     else:
         raise TypeError("Can not calculate bit length of {} {}".format(
             type(v), v))
-
-
-def flen(v):
-    """Bit length of an expression
-
-    Parameters
-    ----------
-    v : int, bool or Value
-
-    Returns
-    -------
-    int
-        Number of bits required to store `v` or available in `v`
-
-    Examples
-    --------
-    >>> flen(f.Signal(8))
-    8
-    >>> flen(0xaa)
-    8
-    """
-    return value_bits_sign(v)[0]
-
diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
@@ -89,11 +89,12 @@ def __gt__(self, other):
     def __ge__(self, other):
         return _Operator(">=", [self, other])
 
+    def __len__(self):
+        from migen.fhdl.bitcontainer import value_bits_sign
+        return value_bits_sign(self)[0]
 
     def __getitem__(self, key):
-        from migen.fhdl.bitcontainer import flen
-
-        n = flen(self)
+        n = len(self)
         if isinstance(key, int):
             if key >= n:
                 raise IndexError
@@ -187,7 +188,7 @@ class Cat(_Value):
     meeting these properties. The bit length of the return value is the sum of
     the bit lengths of the arguments::
 
-        flen(Cat(args)) == sum(flen(arg) for arg in args)
+        len(Cat(args)) == sum(len(arg) for arg in args)
 
     Parameters
     ----------
@@ -210,7 +211,7 @@ class Replicate(_Value):
     An input value is replicated (repeated) several times
     to be used on the RHS of assignments::
 
-        flen(Replicate(s, n)) == flen(s)*n
+        len(Replicate(s, n)) == len(s)*n
 
     Parameters
     ----------
@@ -356,7 +357,7 @@ def like(cls, other, **kwargs):
         other : _Value
             Object to base this Signal on.
 
-        See `migen.fhdl.bitcontainer.value_bits_sign`() for details.
+        See `migen.fhdl.bitcontainer.value_bits_sign` for details.
         """
         from migen.fhdl.bitcontainer import value_bits_sign
         return cls(bits_sign=value_bits_sign(other), **kwargs)

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
@@ -4,7 +4,7 @@
 from migen.fhdl.structure import *
 from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
 from migen.fhdl.tools import *
-from migen.fhdl.bitcontainer import bits_for, flen
+from migen.fhdl.bitcontainer import bits_for
 from migen.fhdl.namer import build_namespace
 from migen.fhdl.conv_output import ConvOutput
 
@@ -36,8 +36,8 @@ def _printsig(ns, s):
         n = "signed "
     else:
         n = ""
-    if flen(s) > 1:
-        n += "[" + str(flen(s)-1) + ":0] "
+    if len(s) > 1:
+        n += "[" + str(len(s)-1) + ":0] "
     n += ns.get_name(s)
     return n
 
@@ -93,7 +93,7 @@ def _printexpr(ns, node):
     elif isinstance(node, _Slice):
         # Verilog does not like us slicing non-array signals...
         if isinstance(node.value, Signal) \
-          and flen(node.value) == 1 \
+          and len(node.value) == 1 \
           and node.start == 0 and node.stop == 1:
               return _printexpr(ns, node.value)
 

diff --git a/migen/genlib/fifo.py b/migen/genlib/fifo.py
@@ -1,13 +1,12 @@
 from migen.fhdl.structure import *
 from migen.fhdl.module import Module
 from migen.fhdl.specials import Memory
-from migen.fhdl.bitcontainer import flen
 from migen.genlib.cdc import NoRetiming, MultiReg, GrayCounter
 from migen.genlib.record import layout_len, Record
 
 
 def _inc(signal, modulo):
-    if modulo == 2**flen(signal):
+    if modulo == 2**len(signal):
         return signal.eq(signal + 1)
     else:
         return If(signal == (modulo - 1),

diff --git a/migen/genlib/misc.py b/migen/genlib/misc.py
@@ -19,8 +19,8 @@ def displacer(signal, shift, output, n=None, reverse=False):
     if shift is None:
         return output.eq(signal)
     if n is None:
-        n = 2**flen(shift)
-    w = flen(signal)
+        n = 2**len(shift)
+    w = len(signal)
     if reverse:
         r = reversed(range(n))
     else:
@@ -33,8 +33,8 @@ def chooser(signal, shift, output, n=None, reverse=False):
     if shift is None:
         return output.eq(signal)
     if n is None:
-        n = 2**flen(shift)
-    w = flen(output)
+        n = 2**len(shift)
+    w = len(output)
     cases = {}
     for i in range(n):
         if reverse:

diff --git a/migen/sim/core.py b/migen/sim/core.py
@@ -4,7 +4,6 @@
 from migen.fhdl.structure import (_Value, _Statement,
                                   _Operator, _Slice, _ArrayProxy,
                                   _Assign, _Fragment)
-from migen.fhdl.bitcontainer import flen
 from migen.fhdl.tools import list_signals, list_targets, insert_resets
 from migen.fhdl.simplify import MemoryToArray
 from migen.fhdl.specials import _MemoryLocation
@@ -123,7 +122,7 @@ def eval(self, node, postcommit=False):
             shift = 0
             r = 0
             for element in node.l:
-                nbits = flen(element)
+                nbits = len(element)
                 # make value always positive
                 r |= (self.eval(element, postcommit) & (2**nbits-1)) << shift
                 shift += nbits
@@ -158,7 +157,7 @@ def assign(self, node, value):
             self.modifications[node] = value
         elif isinstance(node, Cat):
             for element in node.l:
-                nbits = flen(element)
+                nbits = len(element)
                 self.assign(element, value & (2**nbits-1))
                 value >>= nbits
         elif isinstance(node, _Slice):

diff --git a/migen/sim/vcd.py b/migen/sim/vcd.py
@@ -1,6 +1,5 @@
 from itertools import count
 
-from migen.fhdl.bitcontainer import flen
 from migen.fhdl.namer import build_namespace
 
 
@@ -30,7 +29,7 @@ def __init__(self, filename, signals):
                 code = next(codes)
                 self.codes[signal] = code
                 self.fo.write("$var wire {len} {code} {name} $end\n"
-                              .format(name=name, code=code, len=flen(signal)))
+                              .format(name=name, code=code, len=len(signal)))
             self.fo.write("$dumpvars\n")
             for signal in signals:
                 value = signal.reset.value
@@ -43,7 +42,7 @@ def __init__(self, filename, signals):
             raise
 
     def _write_value(self, signal, value):
-        l = flen(signal)
+        l = len(signal)
         if value < 0:
             value += 2**l
         if l > 1:

diff --git a/migen/test/test_coding.py b/migen/test/test_coding.py
@@ -12,9 +12,9 @@ def __init__(self):
             self.submodules.dut = Encoder(8)
 
     def test_sizes(self):
-        self.assertEqual(flen(self.tb.dut.i), 8)
-        self.assertEqual(flen(self.tb.dut.o), 3)
-        self.assertEqual(flen(self.tb.dut.n), 1)
+        self.assertEqual(len(self.tb.dut.i), 8)
+        self.assertEqual(len(self.tb.dut.o), 3)
+        self.assertEqual(len(self.tb.dut.n), 1)
 
     def test_run_sequence(self):
         seq = list(range(1<<8))
@@ -36,9 +36,9 @@ def __init__(self):
             self.submodules.dut = PriorityEncoder(8)
 
     def test_sizes(self):
-        self.assertEqual(flen(self.tb.dut.i), 8)
-        self.assertEqual(flen(self.tb.dut.o), 3)
-        self.assertEqual(flen(self.tb.dut.n), 1)
+        self.assertEqual(len(self.tb.dut.i), 8)
+        self.assertEqual(len(self.tb.dut.o), 3)
+        self.assertEqual(len(self.tb.dut.n), 1)
 
     def test_run_sequence(self):
         seq = list(range(1<<8))
@@ -64,9 +64,9 @@ def __init__(self):
             self.submodules.dut = Decoder(8)
 
     def test_sizes(self):
-        self.assertEqual(flen(self.tb.dut.i), 3)
-        self.assertEqual(flen(self.tb.dut.o), 8)
-        self.assertEqual(flen(self.tb.dut.n), 1)
+        self.assertEqual(len(self.tb.dut.i), 3)
+        self.assertEqual(len(self.tb.dut.o), 8)
+        self.assertEqual(len(self.tb.dut.n), 1)
 
     def test_run_sequence(self):
         seq = list(range(8*2))
@@ -91,9 +91,9 @@ def __init__(self):
             self.submodules.dut = PriorityEncoder(1)
 
     def test_sizes(self):
-        self.assertEqual(flen(self.tb.dut.i), 1)
-        self.assertEqual(flen(self.tb.dut.o), 1)
-        self.assertEqual(flen(self.tb.dut.n), 1)
+        self.assertEqual(len(self.tb.dut.i), 1)
+        self.assertEqual(len(self.tb.dut.o), 1)
+        self.assertEqual(len(self.tb.dut.n), 1)
 
     def test_run_sequence(self):
         seq = list(range(1))

diff --git a/migen/test/test_fifo.py b/migen/test/test_fifo.py
@@ -20,8 +20,8 @@ def __init__(self):
             ]
 
     def test_sizes(self):
-        self.assertEqual(flen(self.tb.dut.din_bits), 64)
-        self.assertEqual(flen(self.tb.dut.dout_bits), 64)
+        self.assertEqual(len(self.tb.dut.din_bits), 64)
+        self.assertEqual(len(self.tb.dut.dout_bits), 64)
 
     def test_run_sequence(self):
         seq = list(range(20))

diff --git a/migen/test/test_size.py b/migen/test/test_size.py
@@ -13,10 +13,7 @@ def setUp(self):
         self.j = C(-127)
         self.s = Signal((13, True))
 
-    def test_flen(self):
-        self.assertEqual(flen(self.s), 13)
-        self.assertEqual(flen(self.i), 8)
-        self.assertEqual(flen(self.j), 8)
-
-    def test_flen_type(self):
-        self.assertRaises(TypeError, flen, [])
+    def test_len(self):
+        self.assertEqual(len(self.s), 13)
+        self.assertEqual(len(self.i), 8)
+        self.assertEqual(len(self.j), 8)
diff --git a/migen/test/test_sort.py b/migen/test/test_sort.py
@@ -16,14 +16,14 @@ def test_sizes(self):
         self.assertEqual(len(self.tb.dut.i), 8)
         self.assertEqual(len(self.tb.dut.o), 8)
         for i in range(8):
-            self.assertEqual(flen(self.tb.dut.i[i]), 4)
-            self.assertEqual(flen(self.tb.dut.o[i]), 4)
+            self.assertEqual(len(self.tb.dut.i[i]), 4)
+            self.assertEqual(len(self.tb.dut.o[i]), 4)
 
     def test_sort(self):
         def gen():
             for repeat in range(20):
                 for i in self.tb.dut.i:
-                    yield i.eq(randrange(1<<flen(i)))
+                    yield i.eq(randrange(1<<len(i)))
                 yield
                 self.assertEqual(sorted((yield self.tb.dut.i)),
                                  (yield self.tb.dut.o))