Skip to content

Commit da425d1

Browse files
sbourdeauducqsbourdeauducq
committedSep 26, 2015
add stream, fix CPUs and more imports. simple target boots on ppro.
·
0.120.1
1 parent 75ef2f9 commit da425d1

File tree

12 files changed

+159
-25
lines changed

12 files changed

+159
-25
lines changed
 

Diff for: ‎make.py

+11-11
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,12 @@
77
import struct
88
import shutil
99

10-
from mibuild.tools import write_to_file
10+
from migen.build.tools import write_to_file
1111
from migen.util.misc import autotype
1212
from migen.fhdl import simplify
1313

14-
from misoc.soc import cpuif
15-
from misoc.mem.sdram.phy import initsequence
14+
from misoc.integration import cpu_interface
15+
from misoc.integration import sdram_init
1616

1717
from misoc_import import misoc_import
1818

@@ -81,7 +81,7 @@ def _get_args():
8181
raise ValueError("Target has no default platform, specify a platform with -p your_platform")
8282
else:
8383
platform_name = args.platform
84-
platform_module = misoc_import("mibuild.platforms", external_platform, platform_name)
84+
platform_module = misoc_import("migen.build.platforms", external_platform, platform_name)
8585
platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
8686
platform = platform_module.Platform(**platform_kwargs)
8787
if args.external:
@@ -155,25 +155,25 @@ def _get_args():
155155
""".format(platform_name, args.target, top_class.__name__, soc.cpu_type)
156156
genhdir = os.path.join("software", "include", "generated")
157157
if soc.cpu_type != "none":
158-
cpu_mak = cpuif.get_cpu_mak(soc.cpu_type)
158+
cpu_mak = cpu_interface.get_cpu_mak(soc.cpu_type)
159159
write_to_file(os.path.join(genhdir, "cpu.mak"), cpu_mak)
160-
linker_output_format = cpuif.get_linker_output_format(soc.cpu_type)
160+
linker_output_format = cpu_interface.get_linker_output_format(soc.cpu_type)
161161
write_to_file(os.path.join(genhdir, "output_format.ld"), linker_output_format)
162162

163-
linker_regions = cpuif.get_linker_regions(memory_regions)
163+
linker_regions = cpu_interface.get_linker_regions(memory_regions)
164164
write_to_file(os.path.join(genhdir, "regions.ld"), boilerplate + linker_regions)
165165

166166
for sdram_phy in ["sdrphy", "ddrphy"]:
167167
if hasattr(soc, sdram_phy):
168-
sdram_phy_header = initsequence.get_sdram_phy_header(getattr(soc, sdram_phy).settings)
168+
sdram_phy_header = sdram_init.get_sdram_phy_header(getattr(soc, sdram_phy).settings)
169169
write_to_file(os.path.join(genhdir, "sdram_phy.h"), boilerplate + sdram_phy_header)
170-
mem_header = cpuif.get_mem_header(memory_regions, getattr(soc, "flash_boot_address", None))
170+
mem_header = cpu_interface.get_mem_header(memory_regions, getattr(soc, "flash_boot_address", None))
171171
write_to_file(os.path.join(genhdir, "mem.h"), boilerplate + mem_header)
172-
csr_header = cpuif.get_csr_header(csr_regions, soc.get_constants())
172+
csr_header = cpu_interface.get_csr_header(csr_regions, soc.get_constants())
173173
write_to_file(os.path.join(genhdir, "csr.h"), boilerplate + csr_header)
174174

175175
if actions["build-csr-csv"]:
176-
csr_csv = cpuif.get_csr_csv(csr_regions)
176+
csr_csv = cpu_interface.get_csr_csv(csr_regions)
177177
write_to_file(args.csr_csv, csr_csv)
178178

179179
if actions["build-bios"]:

Diff for: ‎misoc/cores/lm32/__init__.py

+1
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
from misoc.cores.lm32.core import LM32

Diff for: ‎misoc/cores/lm32/core.py

+6-3
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
import os
22

33
from migen import *
4-
from migen.bus import wishbone
4+
5+
from misoc.interconnect import wishbone
56

67

78
class LM32(Module):
@@ -54,10 +55,12 @@ def __init__(self, platform, eba_reset):
5455
]
5556

5657
# add Verilog sources
57-
platform.add_sources(os.path.join("extcores", "lm32", "submodule", "rtl"),
58+
vdir = os.path.join(
59+
os.path.abspath(os.path.dirname(__file__)), "verilog")
60+
platform.add_sources(os.path.join(vdir, "submodule", "rtl"),
5861
"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
5962
"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
6063
"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
6164
"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
6265
"lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
63-
platform.add_verilog_include_path(os.path.join("extcores", "lm32"))
66+
platform.add_verilog_include_path(vdir)

Diff for: ‎misoc/cores/lm32/verilog/submodule

Submodule submodule added at 84b3e3c

Diff for: ‎misoc/cores/mor1kx/__init__.py

+1
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
from misoc.cores.mor1kx.core import MOR1KX

Diff for: ‎misoc/cores/mor1kx/core.py

+6-3
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
import os
22

33
from migen import *
4-
from migen.bus import wishbone
4+
5+
from misoc.interconnect import wishbone
56

67

78
class MOR1KX(Module):
@@ -76,5 +77,7 @@ def __init__(self, platform, reset_pc):
7677
]
7778

7879
# add Verilog sources
79-
platform.add_source_dir(os.path.join("extcores", "mor1kx", "submodule",
80-
"rtl", "verilog"))
80+
vdir = os.path.join(
81+
os.path.abspath(os.path.dirname(__file__)),
82+
"verilog", "rtl", "verilog")
83+
platform.add_source_dir(vdir)

Diff for: ‎misoc/cores/mor1kx/verilog

Submodule verilog added at fb519d0

Diff for: ‎misoc/cores/uart/core.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
from migen import *
22
from migen.genlib.record import Record
3+
from migen.genlib.cdc import MultiReg
34

45
from misoc.interconnect.csr import *
56
from misoc.interconnect.csr_eventmanager import *
6-
# TODO: from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
7-
# TODO: remove dataflow?
7+
from misoc.interconnect.stream import Source, Sink, SyncFIFO, AsyncFIFO
88

99

1010
class RS232PHYRX(Module):

Diff for: ‎misoc/integration/soc_core.py

+2-1
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,8 @@ def __init__(self, platform, clk_freq,
9494
self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)
9595

9696
if with_csr:
97-
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(csr_data_width, csr_address_width))
97+
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
98+
bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
9899
self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
99100

100101
if with_uart:

Diff for: ‎misoc/interconnect/csr_bus.py

+5-4
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
from migen import *
22
from migen.genlib.record import *
33
from migen.genlib.misc import chooser
4+
from migen.util.misc import xdir
45

56
from misoc.interconnect import csr
67
from misoc.interconnect.csr import CSRStorage
@@ -108,7 +109,7 @@ def __init__(self, description, address=0, bus=None):
108109

109110
###
110111

111-
GenericBank.__init__(self, description, flen(self.bus.dat_w))
112+
csr.GenericBank.__init__(self, description, flen(self.bus.dat_w))
112113

113114
sel = Signal()
114115
self.comb += sel.eq(self.bus.adr[9:] == address)
@@ -154,7 +155,7 @@ def scan(self, ifargs, ifkwargs):
154155
mapaddr = self.address_map(name, memory)
155156
if mapaddr is None:
156157
continue
157-
sram_bus = csr.Interface(*ifargs, **ifkwargs)
158+
sram_bus = Interface(*ifargs, **ifkwargs)
158159
mmap = csr.SRAM(memory, mapaddr, bus=sram_bus)
159160
self.submodules += mmap
160161
csrs += mmap.get_csrs()
@@ -163,8 +164,8 @@ def scan(self, ifargs, ifkwargs):
163164
mapaddr = self.address_map(name, None)
164165
if mapaddr is None:
165166
continue
166-
bank_bus = csr.Interface(*ifargs, **ifkwargs)
167-
rmap = Bank(csrs, mapaddr, bus=bank_bus)
167+
bank_bus = Interface(*ifargs, **ifkwargs)
168+
rmap = CSRBank(csrs, mapaddr, bus=bank_bus)
168169
self.submodules += rmap
169170
self.banks.append((name, csrs, mapaddr, rmap))
170171

Diff for: ‎misoc/interconnect/stream.py

+122
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,122 @@
1+
from migen import *
2+
from migen.genlib.record import *
3+
from migen.genlib import fifo
4+
5+
6+
def _make_m2s(layout):
7+
r = []
8+
for f in layout:
9+
if isinstance(f[1], (int, tuple)):
10+
r.append((f[0], f[1], DIR_M_TO_S))
11+
else:
12+
r.append((f[0], _make_m2s(f[1])))
13+
return r
14+
15+
16+
class EndpointDescription:
17+
def __init__(self, payload_layout, param_layout=[], packetized=False):
18+
self.payload_layout = payload_layout
19+
self.param_layout = param_layout
20+
self.packetized = packetized
21+
22+
def get_full_layout(self):
23+
reserved = {"stb", "ack", "payload", "param", "sop", "eop", "description"}
24+
attributed = set()
25+
for f in self.payload_layout + self.param_layout:
26+
if f[0] in attributed:
27+
raise ValueError(f[0] + " already attributed in payload or param layout")
28+
if f[0] in reserved:
29+
raise ValueError(f[0] + " cannot be used in endpoint layout")
30+
attributed.add(f[0])
31+
32+
full_layout = [
33+
("payload", _make_m2s(self.payload_layout)),
34+
("param", _make_m2s(self.param_layout)),
35+
("stb", 1, DIR_M_TO_S),
36+
("ack", 1, DIR_S_TO_M)
37+
]
38+
if self.packetized:
39+
full_layout += [
40+
("sop", 1, DIR_M_TO_S),
41+
("eop", 1, DIR_M_TO_S)
42+
]
43+
return full_layout
44+
45+
46+
class _Endpoint(Record):
47+
def __init__(self, description_or_layout):
48+
if isinstance(description_or_layout, EndpointDescription):
49+
self.description = description_or_layout
50+
else:
51+
self.description = EndpointDescription(description_or_layout)
52+
Record.__init__(self, self.description.get_full_layout())
53+
54+
def __getattr__(self, name):
55+
try:
56+
return getattr(object.__getattribute__(self, "payload"), name)
57+
except:
58+
return getattr(object.__getattribute__(self, "param"), name)
59+
60+
61+
class Source(_Endpoint):
62+
def connect(self, sink):
63+
return Record.connect(self, sink)
64+
65+
66+
class Sink(_Endpoint):
67+
def connect(self, source):
68+
return source.connect(self)
69+
70+
71+
class _FIFOWrapper(Module):
72+
def __init__(self, fifo_class, layout, depth):
73+
self.sink = Sink(layout)
74+
self.source = Source(layout)
75+
self.busy = Signal()
76+
77+
###
78+
79+
description = self.sink.description
80+
fifo_layout = [
81+
("payload", description.payload_layout),
82+
# Note : Can be optimized by passing parameters
83+
# in another fifo. We will only have one
84+
# data per packet.
85+
("param", description.param_layout)
86+
]
87+
if description.packetized:
88+
fifo_layout += [("sop", 1), ("eop", 1)]
89+
90+
self.submodules.fifo = fifo_class(fifo_layout, depth)
91+
92+
self.comb += [
93+
self.sink.ack.eq(self.fifo.writable),
94+
self.fifo.we.eq(self.sink.stb),
95+
self.fifo.din.payload.eq(self.sink.payload),
96+
self.fifo.din.param.eq(self.sink.param),
97+
98+
self.source.stb.eq(self.fifo.readable),
99+
self.source.payload.eq(self.fifo.dout.payload),
100+
self.source.param.eq(self.fifo.dout.param),
101+
self.fifo.re.eq(self.source.ack)
102+
]
103+
if description.packetized:
104+
self.comb += [
105+
self.fifo.din.sop.eq(self.sink.sop),
106+
self.fifo.din.eop.eq(self.sink.eop),
107+
self.source.sop.eq(self.fifo.dout.sop),
108+
self.source.eop.eq(self.fifo.dout.eop)
109+
]
110+
111+
112+
class SyncFIFO(_FIFOWrapper):
113+
def __init__(self, layout, depth, buffered=False):
114+
_FIFOWrapper.__init__(
115+
self,
116+
fifo.SyncFIFOBuffered if buffered else fifo.SyncFIFO,
117+
layout, depth)
118+
119+
120+
class AsyncFIFO(_FIFOWrapper):
121+
def __init__(self, layout, depth):
122+
_FIFOWrapper.__init__(self, fifo.AsyncFIFO, layout, depth)

Diff for: ‎software/common.mak

+1-1
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ AR_quiet = @echo " AR " $@ && $(AR_normal)
2121
LD_quiet = @echo " LD " $@ && $(LD_normal)
2222
OBJCOPY_quiet = @echo " OBJCOPY " $@ && $(OBJCOPY_normal)
2323

24-
MSC_GIT_ID := $(shell cd $(MSCDIR) && $(PYTHON) -c "from misoc.cpu.identifier import get_id; print(hex(get_id()), end='')")
24+
MSC_GIT_ID := $(shell cd $(MSCDIR) && $(PYTHON) -c "from misoc.cores.identifier import get_id; print(hex(get_id()), end='')")
2525

2626
ifeq ($(V),1)
2727
CC = $(CC_normal)

0 commit comments

Comments
 (0)
Please sign in to comment.