m-labs · Sep 26, 2015 · Sep 26, 2015 · Sep 26, 2015
Showing with 47 additions and 75 deletions.

+11 −14 migen/fhdl/specials.py

+23 −48 migen/fhdl/structure.py

+2 −2 migen/genlib/cdc.py

+10 −10 migen/genlib/io.py

+1 −1 migen/genlib/resetsync.py
diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py
@@ -1,7 +1,7 @@
 from operator import itemgetter
 
 from migen.fhdl.structure import *
-from migen.fhdl.structure import _DUID, _Value
+from migen.fhdl.structure import _Value
 from migen.fhdl.bitcontainer import bits_for, value_bits_sign
 from migen.fhdl.tools import *
 from migen.fhdl.tracer import get_obj_var_name
@@ -12,7 +12,7 @@
     "READ_FIRST", "WRITE_FIRST", "NO_CHANGE"]
 
 
-class Special(_DUID):
+class Special(DUID):
     def iter_expressions(self):
         for x in []:
             yield x
@@ -41,10 +41,10 @@ def list_ios(self, ins, outs, inouts):
 class Tristate(Special):
     def __init__(self, target, o, oe, i=None):
         Special.__init__(self)
-        self.target = target
-        self.o = o
-        self.oe = oe
-        self.i = i
+        self.target = wrap(target)
+        self.o = wrap(o)
+        self.oe = wrap(oe)
+        self.i = wrap(i)
 
     def iter_expressions(self):
         for attr, target_context in [
@@ -84,7 +84,7 @@ def __init__(self, name, expr=None):
             self.name = name
             if expr is None:
                 expr = Signal()
-            self.expr = expr
+            self.expr = wrap(expr)
     class Input(_IO):
         pass
     class Output(_IO):
@@ -94,6 +94,8 @@ class InOut(_IO):
     class Parameter:
         def __init__(self, name, value):
             self.name = name
+            if isinstance(value, (int, bool)):
+                value = Constant(value)
             self.value = value
     class PreformattedParam(str):
         pass
@@ -143,7 +145,7 @@ def emit_verilog(instance, ns, add_data_file):
                     r += ",\n"
                 firstp = False
                 r += "\t." + p.name + "("
-                if isinstance(p.value, (int, bool)):
+                if isinstance(p.value, Constant):
                     r += verilog_printexpr(ns, p.value)[0]
                 elif isinstance(p.value, float):
                     r += str(p.value)
@@ -213,13 +215,8 @@ def emit_verilog(port, ns, add_data_file):
 class _MemoryLocation(_Value):
     def __init__(self, memory, index):
         _Value.__init__(self)
-        if isinstance(index, (bool, int)):
-            index = Constant(index)
-        if not isinstance(index, _Value):
-            raise TypeError("Memory index is not a Migen value: {}"
-                            .format(index))
         self.memory = memory
-        self.index = index
+        self.index = wrap(index)
 
 
 class Memory(Special):

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
@@ -5,15 +5,15 @@
 from migen.util.misc import flat_iteration as _flat_iteration
 
 
-class _DUID:
+class DUID:
     """Deterministic Unique IDentifier"""
     __next_uid = 0
     def __init__(self):
-        self.duid = _DUID.__next_uid
-        _DUID.__next_uid += 1
+        self.duid = DUID.__next_uid
+        DUID.__next_uid += 1
 
 
-class _Value(_DUID):
+class _Value(DUID):
     """Base class for operands
 
     Instances of `_Value` or its subclasses can be operands to
@@ -128,17 +128,21 @@ def __hash__(self):
         raise TypeError("unhashable type: '{}'".format(type(self).__name__))
 
 
+def wrap(value):
+    """Ensures that the passed object is a Migen value. Booleans and integers
+    are automatically wrapped into ``Constant``."""
+    if isinstance(value, (bool, int)):
+        value = Constant(value)
+    if not isinstance(value, _Value):
+        raise TypeError("Object is not a Migen value")
+    return value
+
+
 class _Operator(_Value):
     def __init__(self, op, operands):
         _Value.__init__(self)
         self.op = op
-        self.operands = []
-        for o in operands:
-            if isinstance(o, (bool, int)):
-                o = Constant(o)
-            if not isinstance(o, _Value):
-                raise TypeError("Operand not a Migen value")
-            self.operands.append(o)
+        self.operands = [wrap(o) for o in operands]
 
 
 def Mux(sel, val1, val0):
@@ -164,13 +168,9 @@ def Mux(sel, val1, val0):
 class _Slice(_Value):
     def __init__(self, value, start, stop):
         _Value.__init__(self)
-        if isinstance(value, (bool, int)):
-            value = Constant(value)
-        if not isinstance(value, _Value):
-            raise TypeError("Sliced object is not a Migen value")
         if not isinstance(start, int) or not isinstance(stop, int):
             raise TypeError("Slice boundaries must be integers")
-        self.value = value
+        self.value = wrap(value)
         self.start = start
         self.stop = stop
 
@@ -201,13 +201,7 @@ class Cat(_Value):
     """
     def __init__(self, *args):
         _Value.__init__(self)
-        self.l = []
-        for v in _flat_iteration(args):
-            if isinstance(v, (bool, int)):
-                v = Constant(v)
-            if not isinstance(v, _Value):
-                raise TypeError("Concatenated object is not a Migen value")
-            self.l.append(v)
+        self.l = [wrap(v) for v in _flat_iteration(args)]
 
 
 class Replicate(_Value):
@@ -232,13 +226,9 @@ class Replicate(_Value):
     """
     def __init__(self, v, n):
         _Value.__init__(self)
-        if isinstance(v, (bool, int)):
-            v = Constant(v)
-        if not isinstance(v, _Value):
-            raise TypeError("Replicated object is not a Migen value")
         if not isinstance(n, int) or n < 0:
             raise TypeError("Replication count must be a positive integer")
-        self.v = v
+        self.v = wrap(v)
         self.n = n
 
 
@@ -351,8 +341,7 @@ def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_over
 
     def __setattr__(self, k, v):
         if k == "reset":
-            if isinstance(v, (bool, int)):
-                v = Constant(v)
+            v = wrap(v)
         _Value.__setattr__(self, k, v)
 
     def __repr__(self):
@@ -421,14 +410,8 @@ class _Statement:
 
 class _Assign(_Statement):
     def __init__(self, l, r):
-        if not isinstance(l, _Value):
-            raise TypeError("LHS of assignment is not a Migen value")
-        if isinstance(r, (bool, int)):
-            r = Constant(r)
-        if not isinstance(r, _Value):
-            raise TypeError("RHS of assignment is not a Migen value")
-        self.l = l
-        self.r = r
+        self.l = wrap(l)
+        self.r = wrap(r)
 
 
 def _check_statement(s):
@@ -463,13 +446,9 @@ class If(_Statement):
     ... )
     """
     def __init__(self, cond, *t):
-        if isinstance(cond, (bool, int)):
-            cond = Constant(cond)
-        if not isinstance(cond, _Value):
-            raise TypeError("Test condition is not a Migen value")
         if not _check_statement(t):
             raise TypeError("Not all test body objects are Migen statements")
-        self.cond = cond
+        self.cond = wrap(cond)
         self.t = list(t)
         self.f = []
 
@@ -535,11 +514,7 @@ class Case(_Statement):
     ... })
     """
     def __init__(self, test, cases):
-        if isinstance(test, (bool, int)):
-            test = Constant(test)
-        if not isinstance(test, _Value):
-            raise TypeError("Case test object is not a Migen value")
-        self.test = test
+        self.test = wrap(test)
         self.cases = dict()
         for k, v in cases.items():
             if isinstance(k, (bool, int)):

diff --git a/migen/genlib/cdc.py b/migen/genlib/cdc.py
@@ -39,8 +39,8 @@ def __init__(self, i, o, odomain, n):
 class MultiReg(Special):
     def __init__(self, i, o, odomain="sys", n=2):
         Special.__init__(self)
-        self.i = i
-        self.o = o
+        self.i = wrap(i)
+        self.o = wrap(o)
         self.odomain = odomain
         self.n = n
 

diff --git a/migen/genlib/io.py b/migen/genlib/io.py
@@ -6,9 +6,9 @@
 class DifferentialInput(Special):
     def __init__(self, i_p, i_n, o):
         Special.__init__(self)
-        self.i_p = i_p
-        self.i_n = i_n
-        self.o = o
+        self.i_p = wrap(i_p)
+        self.i_n = wrap(i_n)
+        self.o = wrap(o)
 
     def iter_expressions(self):
         yield self, "i_p", SPECIAL_INPUT
@@ -23,9 +23,9 @@ def lower(dr):
 class DifferentialOutput(Special):
     def __init__(self, i, o_p, o_n):
         Special.__init__(self)
-        self.i = i
-        self.o_p = o_p
-        self.o_n = o_n
+        self.i = wrap(i)
+        self.o_p = wrap(o_p)
+        self.o_n = wrap(o_n)
 
     def iter_expressions(self):
         yield self, "i", SPECIAL_INPUT
@@ -60,10 +60,10 @@ def __init__(self, clk, rst=0):
 class DDRInput(Special):
     def __init__(self, i, o1, o2, clk=ClockSignal()):
         Special.__init__(self)
-        self.i = i
-        self.o1 = o1
-        self.o2 = o2
-        self.clk = clk
+        self.i = wrap(i)
+        self.o1 = wrap(o1)
+        self.o2 = wrap(o2)
+        self.clk = wrap(clk)
 
     def iter_expressions(self):
         yield self, "i", SPECIAL_INPUT

diff --git a/migen/genlib/resetsync.py b/migen/genlib/resetsync.py
@@ -6,7 +6,7 @@ class AsyncResetSynchronizer(Special):
     def __init__(self, cd, async_reset):
         Special.__init__(self)
         self.cd = cd
-        self.async_reset = async_reset
+        self.async_reset = wrap(async_reset)
 
     def iter_expressions(self):
         yield self.cd, "clk", SPECIAL_INPUT