m-labs · Sep 17, 2015 · Sep 17, 2015 · Sep 17, 2015 · Sep 17, 2015
Showing with 30 additions and 70 deletions.

+1 −58 migen/fhdl/bitcontainer.py

+10 −10 migen/fhdl/structure.py

+18 −2 migen/sim.py

+1 −0 migen/test/test_constant.py
diff --git a/migen/fhdl/bitcontainer.py b/migen/fhdl/bitcontainer.py
@@ -1,7 +1,7 @@
 from migen.fhdl import structure as f
 
 
-__all__ = ["log2_int", "bits_for", "flen", "fiter", "fslice", "freversed"]
+__all__ = ["log2_int", "bits_for", "flen", "fiter"]
 
 
 def log2_int(n, need_pow2=True):
@@ -149,60 +149,3 @@ def fiter(v):
         return (v[i] for i in range(flen(v)))
     else:
         raise TypeError("Can not bit-iterate {} {}".format(type(v), v))
-
-
-def fslice(v, s):
-    """Bit slice
-
-    Parameters
-    ----------
-    v : int, bool or Value
-    s : slice or int
-
-    Returns
-    -------
-    int or Value
-        Expression for the slice `s` of `v`.
-
-    Examples
-    --------
-    >>> fslice(f.Signal(2), 1) #doctest: +ELLIPSIS
-    <migen.fhdl.structure._Slice object at 0x...>
-    >>> bin(fslice(0b1101, slice(1, None, 2)))
-    '0b10'
-    >>> fslice(-1, slice(0, 4))
-    1
-    >>> fslice(-7, slice(None))
-    9
-    """
-    if isinstance(v, (bool, int)):
-        if isinstance(s, int):
-            s = slice(s)
-        idx = range(*s.indices(bits_for(v)))
-        return sum(((v >> i) & 1) << j for j, i in enumerate(idx))
-    elif isinstance(v, f.Value):
-        return v[s]
-    else:
-        raise TypeError("Can not bit-slice {} {}".format(type(v), v))
-
-
-def freversed(v):
-    """Bit reverse
-
-    Parameters
-    ----------
-    v : int, bool or Value
-
-    Returns
-    -------
-    int or Value
-        Expression containing the bit reversed input.
-
-    Examples
-    --------
-    >>> freversed(f.Signal(2)) #doctest: +ELLIPSIS
-    <migen.fhdl.structure.Cat object at 0x...>
-    >>> bin(freversed(0b1011))
-    '0b1101'
-    """
-    return fslice(v, slice(None, None, -1))
diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
@@ -1,8 +1,8 @@
-import builtins
-from collections import defaultdict, Iterable
+import builtins as _builtins
+import collections as _collections
 
-from migen.fhdl import tracer
-from migen.util.misc import flat_iteration
+from migen.fhdl import tracer as _tracer
+from migen.util.misc import flat_iteration as _flat_iteration
 
 
 class _DUID:
@@ -202,7 +202,7 @@ class Cat(_Value):
     def __init__(self, *args):
         _Value.__init__(self)
         self.l = []
-        for v in flat_iteration(args):
+        for v in _flat_iteration(args):
             if isinstance(v, (bool, int)):
                 v = Constant(v)
             if not isinstance(v, _Value):
@@ -333,7 +333,7 @@ def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_over
             max -= 1  # make both bounds inclusive
             assert(min < max)
             self.signed = min < 0 or max < 0
-            self.nbits = builtins.max(bits_for(min, self.signed), bits_for(max, self.signed))
+            self.nbits = _builtins.max(bits_for(min, self.signed), bits_for(max, self.signed))
         else:
             assert(min is None and max is None)
             if isinstance(bits_sign, tuple):
@@ -346,7 +346,7 @@ def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_over
         self.variable = variable  # deprecated
         self.reset = reset
         self.name_override = name_override
-        self.backtrace = tracer.trace_back(name)
+        self.backtrace = _tracer.trace_back(name)
         self.related = related
 
     def __setattr__(self, k, v):
@@ -657,7 +657,7 @@ class ClockDomain:
         Reset signal for this domain. Can be driven or used to drive.
     """
     def __init__(self, name=None, reset_less=False):
-        self.name = tracer.get_obj_var_name(name)
+        self.name = _tracer.get_obj_var_name(name)
         if self.name is None:
             raise ValueError("Cannot extract clock domain name from code, need to specify.")
         if self.name.startswith("cd_"):
@@ -711,7 +711,7 @@ def __init__(self, comb=None, sync=None, specials=None, clock_domains=None):
         self.clock_domains = _ClockDomainList(clock_domains)
 
     def __add__(self, other):
-        newsync = defaultdict(list)
+        newsync = _collections.defaultdict(list)
         for k, v in self.sync.items():
             newsync[k] = v[:]
         for k, v in other.sync.items():
@@ -721,7 +721,7 @@ def __add__(self, other):
             self.clock_domains + other.clock_domains)
 
     def __iadd__(self, other):
-        newsync = defaultdict(list)
+        newsync = _collections.defaultdict(list)
         for k, v in self.sync.items():
             newsync[k] = v[:]
         for k, v in other.sync.items():

diff --git a/migen/sim.py b/migen/sim.py
@@ -2,7 +2,8 @@
 from collections import defaultdict
 
 from migen.fhdl.structure import *
-from migen.fhdl.structure import _Operator, _Assign, _Fragment
+from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
+from migen.fhdl.bitcontainer import flen
 from migen.fhdl.tools import list_inputs
 
 
@@ -87,10 +88,25 @@ def eval(self, node):
                     return -operands[0]
                 else:
                     return operands[0] - operands[1]
+            elif node.op == "m":
+                return operands[1] if operands[0] else operands[2]
             else:
                 return str2op[node.op](*operands)
+        elif isinstance(node, _Slice):
+            v = self.eval(node.value)
+            idx = range(node.start, node.stop)
+            return sum(((v >> i) & 1) << j for j, i in enumerate(idx))
+        elif isinstance(node, Cat):
+            shift = 0
+            r = 0
+            for element in node.l:
+                nbits = flen(element)
+                # make value always positive
+                r |= (self.eval(element) & (2**nbits-1)) << shift
+                shift += nbits
+            return r
         else:
-            # TODO: Cat, Slice, Array, ClockSignal, ResetSignal, Memory
+            # TODO: Array, ClockSignal, ResetSignal, Memory
             raise NotImplementedError
 
     def assign(self, signal, value):

diff --git a/migen/test/test_constant.py b/migen/test/test_constant.py
@@ -14,6 +14,7 @@ def __init__(self):
                 (Signal(3), Constant(-1, 7), 7),
                 (Signal(3), Constant(0b10101)[:3], 0b101),
                 (Signal(3), Constant(0b10101)[1:4], 0b10),
+                (Signal(4), Constant(0b1100)[::-1], 0b0011),
             ]
             self.comb += [a.eq(b) for a, b, c in self.sigs]