m-labs · Sep 17, 2015 · Sep 17, 2015 · Sep 17, 2015
Showing with 35 additions and 3 deletions.

+7 −3 doc/fhdl.rst

+28 −0 migen/test/test_constant.py
diff --git a/doc/fhdl.rst b/doc/fhdl.rst
@@ -13,13 +13,17 @@ FHDL is made of several elements, which are briefly explained below. They all ca
 Expressions
 ***********
 
-Integers and booleans
-=====================
+Constants
+=========
+
+The ``Constant`` object represents a constant, HDL-literal integer. It behaves like specifying integers and booleans but also supports slicing and can have a bit width or signedness different from what is implied by the value it represents.
 
-Python integers and booleans can appear in FHDL expressions to represent constant values in a circuit. ``True`` and ``False`` are interpreted as 1 and 0, respectively.
+``True`` and ``False`` are interpreted as 1 and 0, respectively.
 
 Negative integers are explicitly supported. As with MyHDL [countin]_, arithmetic operations return the natural results.
 
+To lighten the syntax, assignments and operators automatically wrap Python integers and booleans into ``Constant``. Additionally, ``Constant`` is aliased to ``C``. The following are valid Migen statements: ``a.eq(0)``, ``a.eq(a + 1)``, ``a.eq(C(42)[0:1])``.
+
 .. [countin] http://www.jandecaluwe.com/hdldesign/counting.html
 
 Signal

diff --git a/migen/test/test_constant.py b/migen/test/test_constant.py
@@ -0,0 +1,28 @@
+import unittest
+
+from migen import *
+from migen.test.support import SimCase
+
+
+class ConstantCase(SimCase, unittest.TestCase):
+    class TestBench(Module):
+        def __init__(self):
+            self.sigs = [
+                (Signal(3), Constant(0), 0),
+                (Signal(3), Constant(5), 5),
+                (Signal(3), Constant(1, 2), 1),
+                (Signal(3), Constant(-1, 7), 7),
+                (Signal(3), Constant(0b10101)[:3], 0b101),
+                (Signal(3), Constant(0b10101)[1:4], 0b10),
+            ]
+            self.comb += [a.eq(b) for a, b, c in self.sigs]
+
+    def test_comparisons(self):
+        def gen():
+            for s, l, v in self.tb.sigs:
+                s = yield s
+                self.assertEqual(
+                    s, int(v),
+                    "got {}, want {} from literal {}".format(
+                        s, v, l))
+        self.run_with(gen())