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base repository: m-labs/migen
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  • 2 commits
  • 2 files changed
  • 2 contributors

Commits on Sep 19, 2015

  1. sim: remove unneeded import

    @sbourdeauducq
    sbourdeauducq committed Sep 19, 2015
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    bfcc8f9 View commit details

  2. migen/genlib/cdc: fix BusSynchronizer 

    ping/pong token can be lost when:
- source clock domain starts before destination clock domain.
- a clock domain stops.

This fix add a timeout to detect such situation and create another token.
    @enjoy-digital @sbourdeauducq
    enjoy-digital authored and sbourdeauducq committed Sep 19, 2015
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    563231f View commit details
Showing with 5 additions and 3 deletions.
  1. +5 −2 migen/genlib/cdc.py
  2. +0 −1 migen/sim.py
7 changes: 5 additions & 2 deletions migen/genlib/cdc.py
View file
Original file line number Diff line number Diff line change
@@ -2,6 +2,7 @@
from migen.fhdl.module import Module
from migen.fhdl.specials import Special
from migen.fhdl.bitcontainer import value_bits_sign
from migen.genlib.misc import WaitTimer


class NoRetiming(Special):
@@ -88,7 +89,7 @@ class BusSynchronizer(Module):
Ensures that all the bits form a single word that was present
synchronously in the input clock domain (unlike direct use of
``MultiReg``)."""
def __init__(self, width, idomain, odomain):
def __init__(self, width, idomain, odomain, timeout=128):
self.i = Signal(width)
self.o = Signal(width)

@@ -102,8 +103,10 @@ def __init__(self, width, idomain, odomain):
sync_i += starter.eq(0)
self.submodules._ping = PulseSynchronizer(idomain, odomain)
self.submodules._pong = PulseSynchronizer(odomain, idomain)
self.submodules._timeout = WaitTimer(timeout)
self.comb += [
self._ping.i.eq(starter | self._pong.o),
self._timeout.wait.eq(~self._ping.i),
self._ping.i.eq(starter | self._pong.o | self._timeout.done),
self._pong.i.eq(self._ping.i)
]

1 change: 0 additions & 1 deletion migen/sim.py
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,4 @@
import operator
from collections import defaultdict

from migen.fhdl.structure import *
from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment