m-labs · Sep 24, 2015 · Sep 24, 2015 · Sep 24, 2015
diff --git a/.gitmodules b/.gitmodules
@@ -1,8 +1,8 @@
-[submodule "misoc/lm32/verilog/submodule"]
-	path = misoc/lm32/verilog/submodule
+[submodule "misoc/cores/lm32/verilog/submodule"]
+	path = misoc/cores/lm32/verilog/submodule
 	url = https://github.com/m-labs/lm32.git
-[submodule "misoc/mor1kx/verilog"]
-	path = misoc/mor1kx/verilog
+[submodule "misoc/cores/mor1kx/verilog"]
+	path = misoc/cores/mor1kx/verilog
 	url = https://github.com/openrisc/mor1kx.git
 [submodule "software/compiler-rt"]
 	path = software/compiler-rt

diff --git a/misoc/liteethmini/__init__.py → misoc/cores/__init__.py b/misoc/liteethmini/__init__.py → misoc/cores/__init__.py
diff --git a/misoc/mem/sdram/phy/dfii.py → misoc/cores/dfii.py b/misoc/mem/sdram/phy/dfii.py → misoc/cores/dfii.py
diff --git a/misoc/dvisampler/__init__.py → misoc/cores/dvi_sampler/__init__.py b/misoc/dvisampler/__init__.py → misoc/cores/dvi_sampler/__init__.py
diff --git a/misoc/dvisampler/analysis.py → misoc/cores/dvi_sampler/analysis.py b/misoc/dvisampler/analysis.py → misoc/cores/dvi_sampler/analysis.py
diff --git a/misoc/dvisampler/chansync.py → misoc/cores/dvi_sampler/chansync.py b/misoc/dvisampler/chansync.py → misoc/cores/dvi_sampler/chansync.py
diff --git a/misoc/dvisampler/charsync.py → misoc/cores/dvi_sampler/charsync.py b/misoc/dvisampler/charsync.py → misoc/cores/dvi_sampler/charsync.py
diff --git a/misoc/dvisampler/clocking.py → misoc/cores/dvi_sampler/clocking.py b/misoc/dvisampler/clocking.py → misoc/cores/dvi_sampler/clocking.py
diff --git a/misoc/dvisampler/common.py → misoc/cores/dvi_sampler/common.py b/misoc/dvisampler/common.py → misoc/cores/dvi_sampler/common.py
diff --git a/misoc/dvisampler/core.py → misoc/cores/dvi_sampler/core.py b/misoc/dvisampler/core.py → misoc/cores/dvi_sampler/core.py
diff --git a/misoc/dvisampler/datacapture.py → misoc/cores/dvi_sampler/datacapture.py b/misoc/dvisampler/datacapture.py → misoc/cores/dvi_sampler/datacapture.py
diff --git a/misoc/dvisampler/debug.py → misoc/cores/dvi_sampler/debug.py b/misoc/dvisampler/debug.py → misoc/cores/dvi_sampler/debug.py
diff --git a/misoc/dvisampler/decoding.py → misoc/cores/dvi_sampler/decoding.py b/misoc/dvisampler/decoding.py → misoc/cores/dvi_sampler/decoding.py
diff --git a/misoc/dvisampler/dma.py → misoc/cores/dvi_sampler/dma.py b/misoc/dvisampler/dma.py → misoc/cores/dvi_sampler/dma.py
diff --git a/misoc/dvisampler/edid.py → misoc/cores/dvi_sampler/edid.py b/misoc/dvisampler/edid.py → misoc/cores/dvi_sampler/edid.py
diff --git a/misoc/dvisampler/wer.py → misoc/cores/dvi_sampler/wer.py b/misoc/dvisampler/wer.py → misoc/cores/dvi_sampler/wer.py
diff --git a/misoc/framebuffer/__init__.py → misoc/cores/framebuffer/__init__.py b/misoc/framebuffer/__init__.py → misoc/cores/framebuffer/__init__.py
diff --git a/misoc/framebuffer/core.py → misoc/cores/framebuffer/core.py b/misoc/framebuffer/core.py → misoc/cores/framebuffer/core.py
diff --git a/misoc/framebuffer/dvi.py → misoc/cores/framebuffer/dvi.py b/misoc/framebuffer/dvi.py → misoc/cores/framebuffer/dvi.py
diff --git a/misoc/framebuffer/format.py → misoc/cores/framebuffer/format.py b/misoc/framebuffer/format.py → misoc/cores/framebuffer/format.py
diff --git a/misoc/framebuffer/phy.py → misoc/cores/framebuffer/phy.py b/misoc/framebuffer/phy.py → misoc/cores/framebuffer/phy.py
diff --git a/misoc/gpio.py → misoc/cores/gpio.py b/misoc/gpio.py → misoc/cores/gpio.py
diff --git a/misoc/identifier.py → misoc/cores/identifier.py b/misoc/identifier.py → misoc/cores/identifier.py
diff --git a/misoc/liteethmini/mac/frontend/__init__.py → misoc/cores/lasmicon/__init__.py b/misoc/liteethmini/mac/frontend/__init__.py → misoc/cores/lasmicon/__init__.py
diff --git a/misoc/mem/sdram/core/lasmicon/bankmachine.py → misoc/cores/lasmicon/bankmachine.py b/misoc/mem/sdram/core/lasmicon/bankmachine.py → misoc/cores/lasmicon/bankmachine.py
diff --git a/misoc/mem/sdram/core/lasmicon/__init__.py → misoc/cores/lasmicon/core.py b/misoc/mem/sdram/core/lasmicon/__init__.py → misoc/cores/lasmicon/core.py
@@ -12,8 +12,7 @@ def __init__(self, req_queue_size=8,
             read_time=32, write_time=16,
             l2_size=8192,
             with_bandwidth=False,
-            with_memtest=False,
-            with_refresh=True):
+            with_memtest=False):
         self.req_queue_size = req_queue_size
         self.read_time = read_time
         self.write_time = write_time
@@ -23,7 +22,6 @@ def __init__(self, req_queue_size=8,
         else:
             self.with_bandwidth = with_bandwidth
         self.with_memtest = with_memtest
-        self.with_refresh = with_refresh
 
 
 class LASMIcon(Module):
@@ -50,7 +48,7 @@ def __init__(self, phy_settings, geom_settings, timing_settings, controller_sett
         ###
 
         self.submodules.refresher = Refresher(geom_settings.addressbits, geom_settings.bankbits,
-            timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC, enabled=controller_settings.with_refresh)
+            timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC)
         self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, controller_settings, address_align, i,
                 getattr(self.lasmic, "bank"+str(i)))
             for i in range(2**geom_settings.bankbits)]

diff --git a/misoc/mem/sdram/core/lasmicon/multiplexer.py → misoc/cores/lasmicon/multiplexer.py b/misoc/mem/sdram/core/lasmicon/multiplexer.py → misoc/cores/lasmicon/multiplexer.py
diff --git a/misoc/mem/sdram/core/lasmicon/perf.py → misoc/cores/lasmicon/perf.py b/misoc/mem/sdram/core/lasmicon/perf.py → misoc/cores/lasmicon/perf.py
diff --git a/misoc/cores/lasmicon/refresher.py b/misoc/cores/lasmicon/refresher.py
@@ -0,0 +1,69 @@
+from migen import *
+from migen.genlib.misc import timeline
+from migen.genlib.fsm import FSM
+
+from misoc.mem.sdram.core.lasmicon.multiplexer import *
+
+
+class Refresher(Module):
+    def __init__(self, a, ba, tRP, tREFI, tRFC):
+        self.req = Signal()
+        self.ack = Signal()  # 1st command 1 cycle after assertion of ack
+        self.cmd = CommandRequest(a, ba)
+
+        ###
+
+        # Refresh sequence generator:
+        # PRECHARGE ALL --(tRP)--> AUTO REFRESH --(tRFC)--> done
+        seq_start = Signal()
+        seq_done = Signal()
+        self.sync += [
+            self.cmd.a.eq(2**10),
+            self.cmd.ba.eq(0),
+            self.cmd.cas_n.eq(1),
+            self.cmd.ras_n.eq(1),
+            self.cmd.we_n.eq(1),
+            seq_done.eq(0)
+        ]
+        self.sync += timeline(seq_start, [
+            (1, [
+                self.cmd.ras_n.eq(0),
+                self.cmd.we_n.eq(0)
+            ]),
+            (1+tRP, [
+                self.cmd.cas_n.eq(0),
+                self.cmd.ras_n.eq(0)
+            ]),
+            (1+tRP+tRFC, [
+                seq_done.eq(1)
+            ])
+        ])
+
+        # Periodic refresh counter
+        counter = Signal(max=tREFI)
+        start = Signal()
+        self.sync += [
+            start.eq(0),
+            If(counter == 0,
+                start.eq(1),
+                counter.eq(tREFI - 1)
+            ).Else(
+                counter.eq(counter - 1)
+            )
+        ]
+
+        # Control FSM
+        fsm = FSM()
+        self.submodules += fsm
+        fsm.act("IDLE", If(start, NextState("WAIT_GRANT")))
+        fsm.act("WAIT_GRANT",
+            self.req.eq(1),
+            If(self.ack,
+                seq_start.eq(1),
+                NextState("WAIT_SEQ")
+            )
+        )
+        fsm.act("WAIT_SEQ",
+            self.req.eq(1),
+            If(seq_done, NextState("IDLE"))
+        )
diff --git a/misoc/mem/sdram/test/bankmachine_tb.py → misoc/cores/lasmicon/test_bankmachine.py b/misoc/mem/sdram/test/bankmachine_tb.py → misoc/cores/lasmicon/test_bankmachine.py
@@ -4,7 +4,7 @@
 from misoc.mem.sdram.code import lasmibus
 from misoc.mem.sdram.core.lasmicon.bankmachine import *
 
-from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger
+from test_common import sdram_phy, sdram_geom, sdram_timing, CommandLogger
 
 
 def my_generator():

diff --git a/misoc/mem/sdram/test/common.py → misoc/cores/lasmicon/test_common.py b/misoc/mem/sdram/test/common.py → misoc/cores/lasmicon/test_common.py
diff --git a/misoc/mem/sdram/test/lasmicon_df_tb.py → misoc/cores/lasmicon/test_df.py b/misoc/mem/sdram/test/lasmicon_df_tb.py → misoc/cores/lasmicon/test_df.py
@@ -5,7 +5,7 @@
 from misoc.mem.sdram.core.lasmicon import *
 from misoc.mem.sdram.frontend import dma_lasmi
 
-from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
+from test_common import sdram_phy, sdram_geom, sdram_timing, DFILogger
 
 
 class TB(Module):

diff --git a/misoc/mem/sdram/test/lasmicon_tb.py → misoc/cores/lasmicon/test_lasmi.py b/misoc/mem/sdram/test/lasmicon_tb.py → misoc/cores/lasmicon/test_lasmi.py
@@ -4,7 +4,7 @@
 from misoc.mem.sdram.core import lasmibus
 from misoc.mem.sdram.core.lasmicon import *
 
-from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
+from test_common import sdram_phy, sdram_geom, sdram_timing, DFILogger
 
 
 def my_generator_r(n):

diff --git a/misoc/mem/sdram/test/refresher.py → misoc/cores/lasmicon/test_refresher.py b/misoc/mem/sdram/test/refresher.py → misoc/cores/lasmicon/test_refresher.py
diff --git a/misoc/mem/sdram/test/lasmicon_wb.py → misoc/cores/lasmicon/test_wb.py b/misoc/mem/sdram/test/lasmicon_wb.py → misoc/cores/lasmicon/test_wb.py
@@ -7,7 +7,7 @@
 from misoc.mem.sdram.core.lasmicon import *
 from misoc.mem.sdram.frontend import wishbone2lasmi
 
-from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
+from test_common import sdram_phy, sdram_geom, sdram_timing, DFILogger
 
 l2_size = 8192  # in bytes
 

diff --git a/misoc/liteethmini/LICENSE → misoc/cores/liteeth_mini/LICENSE b/misoc/liteethmini/LICENSE → misoc/cores/liteeth_mini/LICENSE
diff --git a/misoc/liteethmini/README → misoc/cores/liteeth_mini/README b/misoc/liteethmini/README → misoc/cores/liteeth_mini/README
diff --git a/misoc/mem/sdram/frontend/__init__.py → misoc/cores/liteeth_mini/__init__.py b/misoc/mem/sdram/frontend/__init__.py → misoc/cores/liteeth_mini/__init__.py
diff --git a/misoc/liteethmini/common.py → misoc/cores/liteeth_mini/common.py b/misoc/liteethmini/common.py → misoc/cores/liteeth_mini/common.py
diff --git a/misoc/liteethmini/mac/__init__.py → misoc/cores/liteeth_mini/mac/__init__.py b/misoc/liteethmini/mac/__init__.py → misoc/cores/liteeth_mini/mac/__init__.py
diff --git a/misoc/liteethmini/mac/core/__init__.py → ...c/cores/liteeth_mini/mac/core/__init__.py b/misoc/liteethmini/mac/core/__init__.py → ...c/cores/liteeth_mini/mac/core/__init__.py
diff --git a/misoc/liteethmini/mac/core/crc.py → misoc/cores/liteeth_mini/mac/core/crc.py b/misoc/liteethmini/mac/core/crc.py → misoc/cores/liteeth_mini/mac/core/crc.py
diff --git a/misoc/liteethmini/mac/core/gap.py → misoc/cores/liteeth_mini/mac/core/gap.py b/misoc/liteethmini/mac/core/gap.py → misoc/cores/liteeth_mini/mac/core/gap.py
diff --git a/misoc/liteethmini/mac/core/last_be.py → misoc/cores/liteeth_mini/mac/core/last_be.py b/misoc/liteethmini/mac/core/last_be.py → misoc/cores/liteeth_mini/mac/core/last_be.py
diff --git a/misoc/liteethmini/mac/core/padding.py → misoc/cores/liteeth_mini/mac/core/padding.py b/misoc/liteethmini/mac/core/padding.py → misoc/cores/liteeth_mini/mac/core/padding.py
diff --git a/misoc/liteethmini/mac/core/preamble.py → ...c/cores/liteeth_mini/mac/core/preamble.py b/misoc/liteethmini/mac/core/preamble.py → ...c/cores/liteeth_mini/mac/core/preamble.py
diff --git a/misoc/mem/sdram/phy/__init__.py → ...res/liteeth_mini/mac/frontend/__init__.py b/misoc/mem/sdram/phy/__init__.py → ...res/liteeth_mini/mac/frontend/__init__.py
diff --git a/misoc/liteethmini/mac/frontend/sram.py → ...c/cores/liteeth_mini/mac/frontend/sram.py b/misoc/liteethmini/mac/frontend/sram.py → ...c/cores/liteeth_mini/mac/frontend/sram.py
diff --git a/misoc/liteethmini/mac/frontend/wishbone.py → ...res/liteeth_mini/mac/frontend/wishbone.py b/misoc/liteethmini/mac/frontend/wishbone.py → ...res/liteeth_mini/mac/frontend/wishbone.py
diff --git a/misoc/liteethmini/phy/__init__.py → misoc/cores/liteeth_mini/phy/__init__.py b/misoc/liteethmini/phy/__init__.py → misoc/cores/liteeth_mini/phy/__init__.py
diff --git a/misoc/liteethmini/phy/gmii.py → misoc/cores/liteeth_mini/phy/gmii.py b/misoc/liteethmini/phy/gmii.py → misoc/cores/liteeth_mini/phy/gmii.py
diff --git a/misoc/liteethmini/phy/gmii_mii.py → misoc/cores/liteeth_mini/phy/gmii_mii.py b/misoc/liteethmini/phy/gmii_mii.py → misoc/cores/liteeth_mini/phy/gmii_mii.py
diff --git a/misoc/liteethmini/phy/loopback.py → misoc/cores/liteeth_mini/phy/loopback.py b/misoc/liteethmini/phy/loopback.py → misoc/cores/liteeth_mini/phy/loopback.py
diff --git a/misoc/liteethmini/phy/mii.py → misoc/cores/liteeth_mini/phy/mii.py b/misoc/liteethmini/phy/mii.py → misoc/cores/liteeth_mini/phy/mii.py
diff --git a/misoc/liteethmini/phy/s6rgmii.py → misoc/cores/liteeth_mini/phy/s6rgmii.py b/misoc/liteethmini/phy/s6rgmii.py → misoc/cores/liteeth_mini/phy/s6rgmii.py
diff --git a/misoc/liteethmini/phy/sim.py → misoc/cores/liteeth_mini/phy/sim.py b/misoc/liteethmini/phy/sim.py → misoc/cores/liteeth_mini/phy/sim.py
diff --git a/misoc/lm32/core.py → misoc/cores/lm32/core.py b/misoc/lm32/core.py → misoc/cores/lm32/core.py
diff --git a/misoc/lm32/verilog/lm32_config.v → misoc/cores/lm32/verilog/lm32_config.v b/misoc/lm32/verilog/lm32_config.v → misoc/cores/lm32/verilog/lm32_config.v
diff --git a/misoc/cores/minicon/__init__.py b/misoc/cores/minicon/__init__.py
@@ -0,0 +1 @@
+from misoc.cores.minicon.core import Minicon, MiniconSettings
diff --git a/misoc/mem/sdram/core/minicon/__init__.py → misoc/cores/minicon/core.py b/misoc/mem/sdram/core/minicon/__init__.py → misoc/cores/minicon/core.py
@@ -96,7 +96,6 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
                                 address_align)
 
         # Manage banks
-        bank_open = Signal()
         bank_idle = Signal()
         bank_hit = Signal()
 

diff --git a/misoc/mem/sdram/test/minicon_tb.py → misoc/cores/minicon/test.py b/misoc/mem/sdram/test/minicon_tb.py → misoc/cores/minicon/test.py
diff --git a/misoc/mor1kx/__init__.py → misoc/cores/mor1kx/__init__.py b/misoc/mor1kx/__init__.py → misoc/cores/mor1kx/__init__.py
diff --git a/misoc/mor1kx/core.py → misoc/cores/mor1kx/core.py b/misoc/mor1kx/core.py → misoc/cores/mor1kx/core.py
diff --git a/misoc/mxcrg.v → misoc/cores/mxcrg.v b/misoc/mxcrg.v → misoc/cores/mxcrg.v
diff --git a/misoc/norflash16.py → misoc/cores/nor_flash_16.py b/misoc/norflash16.py → misoc/cores/nor_flash_16.py
diff --git a/misoc/mem/sdram/phy/simphy.py → misoc/cores/sdram_model.py b/misoc/mem/sdram/phy/simphy.py → misoc/cores/sdram_model.py
@@ -158,7 +158,6 @@ def __init__(self, module, settings):
 
             # bank reads
             reads = Signal(len(phases))
-            read_data = Signal(data_width)
             cases = {}
             for np, phase in enumerate(phases):
                 self.comb += reads[np].eq(phase.read)

diff --git a/misoc/cores/sdram_phy/__init__.py b/misoc/cores/sdram_phy/__init__.py
@@ -0,0 +1,3 @@
+from misoc.cores.sdramphy.gensdrphy import GENSDRPHY
+from misoc.cores.sdramphy.s6ddrphy import S6HalfRateDDRPHY, S6QuarterRateDDRPHY
+from misoc.cores.sdramphy.k7ddrphy import K7DDRPHY
diff --git a/misoc/mem/sdram/phy/gensdrphy.py → misoc/cores/sdram_phy/gensdrphy.py b/misoc/mem/sdram/phy/gensdrphy.py → misoc/cores/sdram_phy/gensdrphy.py
diff --git a/misoc/mem/sdram/phy/k7ddrphy.py → misoc/cores/sdram_phy/k7ddrphy.py b/misoc/mem/sdram/phy/k7ddrphy.py → misoc/cores/sdram_phy/k7ddrphy.py
diff --git a/misoc/mem/sdram/phy/s6ddrphy.py → misoc/cores/sdram_phy/s6ddrphy.py b/misoc/mem/sdram/phy/s6ddrphy.py → misoc/cores/sdram_phy/s6ddrphy.py
diff --git a/misoc/mem/sdram/module.py → misoc/cores/sdram_settings.py b/misoc/mem/sdram/module.py → misoc/cores/sdram_settings.py
@@ -1,9 +1,21 @@
-# SDRAM memory modules library
-#
-# This library avoid duplications of memory modules definitions in targets and
-# ease SDRAM usage. (User can only select an already existing module or create
-# one for its board and contribute to this library)
-#
+from math import ceil
+from collections import namedtuple
+
+from migen import *
+from misoc.mem import sdram
+
+
+PhySettingsT = namedtuple("PhySettings", "memtype dfi_databits nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency")
+def PhySettings(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, read_latency, write_latency, cwl=0):
+    return PhySettingsT(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, cwl, read_latency, write_latency)
+
+GeomSettingsT = namedtuple("_GeomSettings", "bankbits rowbits colbits addressbits")
+def GeomSettings(bankbits, rowbits, colbits):
+    return GeomSettingsT(bankbits, rowbits, colbits, max(rowbits, colbits))
+
+TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")
+
+
 # TODO:
 #   Try to share the maximum information we can between modules:
 #    - ex: MT46V32M16 and MT46H32M16 are almost identical (V=DDR, H=LPDDR)
@@ -14,11 +26,6 @@
 #    - Modules can have different speedgrades, add support for it (and also add
 #      a check to verify clk_freq is in the supported range)
 
-from math import ceil
-
-from migen import *
-from misoc.mem import sdram
-
 
 class SDRAMModule:
     def __init__(self, clk_freq, memtype, geom_settings, timing_settings):

diff --git a/misoc/mem/sdram/frontend/memtest.py → misoc/cores/sdram_tester.py b/misoc/mem/sdram/frontend/memtest.py → misoc/cores/sdram_tester.py
diff --git a/misoc/spi/__init__.py → misoc/cores/spi/__init__.py b/misoc/spi/__init__.py → misoc/cores/spi/__init__.py
diff --git a/misoc/spi/core.py → misoc/cores/spi/core.py b/misoc/spi/core.py → misoc/cores/spi/core.py
diff --git a/misoc/spi/test.py → misoc/cores/spi/test.py b/misoc/spi/test.py → misoc/cores/spi/test.py
diff --git a/misoc/spiflash.py → misoc/cores/spi_flash.py b/misoc/spiflash.py → misoc/cores/spi_flash.py
diff --git a/misoc/timer.py → misoc/cores/timer.py b/misoc/timer.py → misoc/cores/timer.py
diff --git a/misoc/uart/__init__.py → misoc/cores/uart/__init__.py b/misoc/uart/__init__.py → misoc/cores/uart/__init__.py
diff --git a/misoc/uart/core.py → misoc/cores/uart/core.py b/misoc/uart/core.py → misoc/cores/uart/core.py
diff --git a/misoc/uart/test.py → misoc/cores/uart/test.py b/misoc/uart/test.py → misoc/cores/uart/test.py
diff --git a/misoc/integration/cpuif.py → misoc/integration/cpu_interface.py b/misoc/integration/cpuif.py → misoc/integration/cpu_interface.py
diff --git a/misoc/mem/sdram/phy/initsequence.py → misoc/integration/sdram_init.py b/misoc/mem/sdram/phy/initsequence.py → misoc/integration/sdram_init.py
diff --git a/misoc/integration/soc_sdram.py b/misoc/integration/soc_sdram.py
@@ -2,13 +2,41 @@
 from migen.bus import wishbone
 from migen.genlib.record import *
 
-from misoc.mem.sdram.core import SDRAMCore
 from misoc.mem.sdram.core.lasmicon import LASMIconSettings
 from misoc.mem.sdram.core.minicon import MiniconSettings
 from misoc.mem.sdram.frontend import memtest, wishbone2lasmi
 from misoc.integration.soc_core import SoCCore
 
 
+class SDRAMCore(Module, AutoCSR):
+    def __init__(self, phy, geom_settings, timing_settings, controller_settings, **kwargs):
+        # DFI
+        self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits,
+                phy.settings.dfi_databits, phy.settings.nphases)
+        self.comb += Record.connect(self.dfii.master, phy.dfi)
+
+        # LASMICON
+        if isinstance(controller_settings, lasmicon.LASMIconSettings):
+            self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings,
+                                                                        geom_settings,
+                                                                        timing_settings,
+                                                                        controller_settings,
+                                                                        **kwargs)
+            self.comb += Record.connect(controller.dfi, self.dfii.slave)
+
+            self.submodules.crossbar = lasmixbar.LASMIxbar([controller.lasmic],
+                                                           controller.nrowbits)
+
+        # MINICON
+        elif isinstance(controller_settings, minicon.MiniconSettings):
+            self.submodules.controller = controller = minicon.Minicon(phy.settings,
+                                                                      geom_settings,
+                                                                      timing_settings)
+            self.comb += Record.connect(controller.dfi, self.dfii.slave)
+        else:
+            raise ValueError("Unsupported SDRAM controller type")
+
+
 class SoCSDRAM(SoCCore):
     csr_map = {
         "sdram":           8,

diff --git a/misoc/mem/sdram/phy/dfi.py → misoc/interconnect/dfi.py b/misoc/mem/sdram/phy/dfi.py → misoc/interconnect/dfi.py
diff --git a/misoc/mem/sdram/frontend/dma_lasmi.py → misoc/interconnect/dma_lasmi.py b/misoc/mem/sdram/frontend/dma_lasmi.py → misoc/interconnect/dma_lasmi.py
diff --git a/misoc/mem/sdram/core/lasmibus.py → misoc/interconnect/lasmibus.py b/misoc/mem/sdram/core/lasmibus.py → misoc/interconnect/lasmibus.py
diff --git a/misoc/mem/sdram/core/lasmixbar.py → misoc/interconnect/lasmixbar.py b/misoc/mem/sdram/core/lasmixbar.py → misoc/interconnect/lasmixbar.py
diff --git a/misoc/mem/sdram/frontend/wishbone2lasmi.py → misoc/interconnect/wishbone2lasmi.py b/misoc/mem/sdram/frontend/wishbone2lasmi.py → misoc/interconnect/wishbone2lasmi.py
diff --git a/misoc/mem/sdram/__init__.py b/misoc/mem/sdram/__init__.py
diff --git a/misoc/mem/sdram/core/__init__.py b/misoc/mem/sdram/core/__init__.py
diff --git a/misoc/mem/sdram/core/lasmicon/refresher.py b/misoc/mem/sdram/core/lasmicon/refresher.py
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		from misoc.cores.minicon.core import Minicon, MiniconSettings