reorganization WIP: flatten core structure (SDRAM still needs to be d…

…one)
m-labs · Sep 23, 2015 · 8350916 · 8350916
1 parent 01be953
commit 8350916
Showing 76 changed files with 104 additions and 437 deletions.
diff --git a/.gitmodules b/.gitmodules
@@ -1,8 +1,8 @@
-[submodule "extcores/lm32/submodule"]
-	path = extcores/lm32/submodule
+[submodule "misoc/lm32/verilog/submodule"]
+	path = misoc/lm32/verilog/submodule
 	url = https://github.com/m-labs/lm32.git
-[submodule "extcores/mor1kx/submodule"]
-	path = extcores/mor1kx/submodule
+[submodule "misoc/mor1kx/verilog"]
+	path = misoc/mor1kx/verilog
 	url = https://github.com/openrisc/mor1kx.git
 [submodule "software/compiler-rt"]
 	path = software/compiler-rt

diff --git a/extcores/lm32/submodule b/extcores/lm32/submodule
diff --git a/extcores/mor1kx/submodule b/extcores/mor1kx/submodule
diff --git a/misoc/com/liteethmini/mac/frontend/__init__.py b/misoc/com/liteethmini/mac/frontend/__init__.py
diff --git a/misoc/com/uart/__init__.py b/misoc/com/uart/__init__.py
diff --git a/misoc/com/uart/bridge.py b/misoc/com/uart/bridge.py
diff --git a/misoc/com/uart/phy/__init__.py b/misoc/com/uart/phy/__init__.py
diff --git a/misoc/com/uart/phy/sim.py b/misoc/com/uart/phy/sim.py
diff --git a/misoc/com/uart/software/__init__.py b/misoc/com/uart/software/__init__.py
diff --git a/misoc/com/uart/software/reg.py b/misoc/com/uart/software/reg.py
diff --git a/misoc/com/uart/software/wishbone.py b/misoc/com/uart/software/wishbone.py
diff --git a/misoc/cpu/__init__.py b/misoc/cpu/__init__.py
diff --git a/misoc/dvisampler/__init__.py b/misoc/dvisampler/__init__.py
@@ -0,0 +1 @@
+from misoc.dvisampler.core import DVISampler
diff --git a/misoc/video/dvisampler/analysis.py → misoc/dvisampler/analysis.py b/misoc/video/dvisampler/analysis.py → misoc/dvisampler/analysis.py
@@ -5,7 +5,7 @@
 from migen.bank.description import *
 from migen.flow.actor import *
 
-from misoc.video.dvisampler.common import channel_layout
+from misoc.dvisampler.common import channel_layout
 
 
 class SyncPolarity(Module):

diff --git a/misoc/video/dvisampler/chansync.py → misoc/dvisampler/chansync.py b/misoc/video/dvisampler/chansync.py → misoc/dvisampler/chansync.py
@@ -5,7 +5,7 @@
 from migen.genlib.misc import optree
 from migen.bank.description import *
 
-from misoc.video.dvisampler.common import channel_layout
+from misoc.dvisampler.common import channel_layout
 
 
 class _SyncBuffer(Module):

diff --git a/misoc/video/dvisampler/charsync.py → misoc/dvisampler/charsync.py b/misoc/video/dvisampler/charsync.py → misoc/dvisampler/charsync.py
@@ -3,7 +3,7 @@
 from migen.genlib.misc import optree
 from migen.bank.description import *
 
-from misoc.video.dvisampler.common import control_tokens
+from misoc.dvisampler.common import control_tokens
 
 
 class CharSync(Module, AutoCSR):

diff --git a/misoc/video/dvisampler/clocking.py → misoc/dvisampler/clocking.py b/misoc/video/dvisampler/clocking.py → misoc/dvisampler/clocking.py
diff --git a/misoc/video/dvisampler/common.py → misoc/dvisampler/common.py b/misoc/video/dvisampler/common.py → misoc/dvisampler/common.py
diff --git a/misoc/video/dvisampler/__init__.py → misoc/dvisampler/core.py b/misoc/video/dvisampler/__init__.py → misoc/dvisampler/core.py
@@ -1,15 +1,15 @@
 from migen import *
 from migen.bank.description import AutoCSR
 
-from misoc.video.dvisampler.edid import EDID
-from misoc.video.dvisampler.clocking import Clocking
-from misoc.video.dvisampler.datacapture import DataCapture
-from misoc.video.dvisampler.charsync import CharSync
-from misoc.video.dvisampler.wer import WER
-from misoc.video.dvisampler.decoding import Decoding
-from misoc.video.dvisampler.chansync import ChanSync
-from misoc.video.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
-from misoc.video.dvisampler.dma import DMA
+from misoc.dvisampler.edid import EDID
+from misoc.dvisampler.clocking import Clocking
+from misoc.dvisampler.datacapture import DataCapture
+from misoc.dvisampler.charsync import CharSync
+from misoc.dvisampler.wer import WER
+from misoc.dvisampler.decoding import Decoding
+from misoc.dvisampler.chansync import ChanSync
+from misoc.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
+from misoc.dvisampler.dma import DMA
 
 
 class DVISampler(Module, AutoCSR):

diff --git a/misoc/video/dvisampler/datacapture.py → misoc/dvisampler/datacapture.py b/misoc/video/dvisampler/datacapture.py → misoc/dvisampler/datacapture.py
diff --git a/misoc/video/dvisampler/debug.py → misoc/dvisampler/debug.py b/misoc/video/dvisampler/debug.py → misoc/dvisampler/debug.py
@@ -5,9 +5,9 @@
 from migen.actorlib import structuring, spi
 
 from misoc.mem.sdram.frontend import dma_lasmi
-from misoc.video.dvisampler.edid import EDID
-from misoc.video.dvisampler.clocking import Clocking
-from misoc.video.dvisampler.datacapture import DataCapture
+from misoc.dvisampler.edid import EDID
+from misoc.dvisampler.clocking import Clocking
+from misoc.dvisampler.datacapture import DataCapture
 
 
 class RawDVISampler(Module, AutoCSR):

diff --git a/misoc/video/dvisampler/decoding.py → misoc/dvisampler/decoding.py b/misoc/video/dvisampler/decoding.py → misoc/dvisampler/decoding.py
@@ -1,7 +1,7 @@
 from migen import *
 from migen.genlib.record import Record
 
-from misoc.video.dvisampler.common import control_tokens, channel_layout
+from misoc.dvisampler.common import control_tokens, channel_layout
 
 
 class Decoding(Module):

diff --git a/misoc/video/dvisampler/dma.py → misoc/dvisampler/dma.py b/misoc/video/dvisampler/dma.py → misoc/dvisampler/dma.py
diff --git a/misoc/video/dvisampler/edid.py → misoc/dvisampler/edid.py b/misoc/video/dvisampler/edid.py → misoc/dvisampler/edid.py
diff --git a/misoc/video/dvisampler/wer.py → misoc/dvisampler/wer.py b/misoc/video/dvisampler/wer.py → misoc/dvisampler/wer.py
@@ -3,7 +3,7 @@
 from migen.genlib.misc import optree
 from migen.genlib.cdc import PulseSynchronizer
 
-from misoc.video.dvisampler.common import control_tokens
+from misoc.dvisampler.common import control_tokens
 
 
 class WER(Module, AutoCSR):

diff --git a/misoc/framebuffer/__init__.py b/misoc/framebuffer/__init__.py
@@ -0,0 +1 @@
+from misoc.framebuffer.core import Framebuffer
diff --git a/misoc/video/framebuffer/__init__.py → misoc/framebuffer/core.py b/misoc/video/framebuffer/__init__.py → misoc/framebuffer/core.py
@@ -5,8 +5,8 @@
 from migen.actorlib import structuring, misc
 
 from misoc.mem.sdram.frontend import dma_lasmi
-from misoc.video.framebuffer.format import bpp, pixel_layout, FrameInitiator, VTG
-from misoc.video.framebuffer.phy import Driver
+from misoc.framebuffer.format import bpp, pixel_layout, FrameInitiator, VTG
+from misoc.framebuffer.phy import Driver
 
 
 class Framebuffer(Module, AutoCSR):

diff --git a/misoc/video/framebuffer/dvi.py → misoc/framebuffer/dvi.py b/misoc/video/framebuffer/dvi.py → misoc/framebuffer/dvi.py
diff --git a/misoc/video/framebuffer/format.py → misoc/framebuffer/format.py b/misoc/video/framebuffer/format.py → misoc/framebuffer/format.py
diff --git a/misoc/video/framebuffer/phy.py → misoc/framebuffer/phy.py b/misoc/video/framebuffer/phy.py → misoc/framebuffer/phy.py
@@ -4,8 +4,8 @@
 from migen.bank.description import *
 from migen.flow.actor import *
 
-from misoc.video.framebuffer.format import bpc_phy, phy_layout
-from misoc.video.framebuffer import dvi
+from misoc.framebuffer.format import bpc_phy, phy_layout
+from misoc.framebuffer import dvi
 
 
 class _FIFO(Module):

diff --git a/misoc/com/gpio.py → misoc/gpio.py b/misoc/com/gpio.py → misoc/gpio.py
diff --git a/misoc/cpu/identifier.py → misoc/identifier.py b/misoc/cpu/identifier.py → misoc/identifier.py
diff --git a/misoc/integration/__init__.py b/misoc/integration/__init__.py
@@ -0,0 +1,2 @@
+from misoc.integration.soc_core import SoCCore
+from misoc.integration.soc_sdram import SoCSDRAM
diff --git a/misoc/soc/cpuif.py → misoc/integration/cpuif.py b/misoc/soc/cpuif.py → misoc/integration/cpuif.py
diff --git a/misoc/soc/__init__.py → misoc/integration/soc_core.py b/misoc/soc/__init__.py → misoc/integration/soc_core.py
@@ -4,17 +4,14 @@
 from migen.bank import csrgen
 from migen.bus import wishbone, csr, wishbone2csr
 
-from misoc.com.uart.phy import UARTPHY
-from misoc.com import uart
-from misoc.cpu import lm32, mor1kx
-from misoc.cpu import identifier, timer
+from misoc import lm32, mor1kx, identifier, timer, uart
 
 
 def mem_decoder(address, start=26, end=29):
     return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
 
 
-class SoC(Module):
+class SoCCore(Module):
     csr_map = {
         "crg":        0,  # user
         "uart_phy":   1,  # provided by default (optional)
@@ -102,7 +99,7 @@ def __init__(self, platform, clk_freq,
             self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
 
             if with_uart:
-                self.submodules.uart_phy = UARTPHY(platform.request("serial"), clk_freq, uart_baudrate)
+                self.submodules.uart_phy = uart.RS232PHY(platform.request("serial"), clk_freq, uart_baudrate)
                 self.submodules.uart = uart.UART(self.uart_phy)
 
             if with_identifier:

diff --git a/misoc/soc/sdram.py → misoc/integration/soc_sdram.py b/misoc/soc/sdram.py → misoc/integration/soc_sdram.py
@@ -6,10 +6,10 @@
 from misoc.mem.sdram.core.lasmicon import LASMIconSettings
 from misoc.mem.sdram.core.minicon import MiniconSettings
 from misoc.mem.sdram.frontend import memtest, wishbone2lasmi
-from misoc.soc import SoC
+from misoc.integration.soc_core import SoCCore
 
 
-class SDRAMSoC(SoC):
+class SoCSDRAM(SoCCore):
     csr_map = {
         "sdram":           8,
         "l2_cache":        9,

diff --git a/misoc/com/liteethmini/LICENSE → misoc/liteethmini/LICENSE b/misoc/com/liteethmini/LICENSE → misoc/liteethmini/LICENSE
diff --git a/misoc/com/liteethmini/README → misoc/liteethmini/README b/misoc/com/liteethmini/README → misoc/liteethmini/README
diff --git a/extcores/__init__.py → misoc/liteethmini/__init__.py b/extcores/__init__.py → misoc/liteethmini/__init__.py
diff --git a/misoc/com/liteethmini/common.py → misoc/liteethmini/common.py b/misoc/com/liteethmini/common.py → misoc/liteethmini/common.py
diff --git a/misoc/com/liteethmini/mac/__init__.py → misoc/liteethmini/mac/__init__.py b/misoc/com/liteethmini/mac/__init__.py → misoc/liteethmini/mac/__init__.py
diff --git a/misoc/com/liteethmini/mac/core/__init__.py → misoc/liteethmini/mac/core/__init__.py b/misoc/com/liteethmini/mac/core/__init__.py → misoc/liteethmini/mac/core/__init__.py
diff --git a/misoc/com/liteethmini/mac/core/crc.py → misoc/liteethmini/mac/core/crc.py b/misoc/com/liteethmini/mac/core/crc.py → misoc/liteethmini/mac/core/crc.py
diff --git a/misoc/com/liteethmini/mac/core/gap.py → misoc/liteethmini/mac/core/gap.py b/misoc/com/liteethmini/mac/core/gap.py → misoc/liteethmini/mac/core/gap.py
diff --git a/misoc/com/liteethmini/mac/core/last_be.py → misoc/liteethmini/mac/core/last_be.py b/misoc/com/liteethmini/mac/core/last_be.py → misoc/liteethmini/mac/core/last_be.py
diff --git a/misoc/com/liteethmini/mac/core/padding.py → misoc/liteethmini/mac/core/padding.py b/misoc/com/liteethmini/mac/core/padding.py → misoc/liteethmini/mac/core/padding.py
diff --git a/misoc/com/liteethmini/mac/core/preamble.py → misoc/liteethmini/mac/core/preamble.py b/misoc/com/liteethmini/mac/core/preamble.py → misoc/liteethmini/mac/core/preamble.py
diff --git a/misoc/com/__init__.py → misoc/liteethmini/mac/frontend/__init__.py b/misoc/com/__init__.py → misoc/liteethmini/mac/frontend/__init__.py
diff --git a/misoc/com/liteethmini/mac/frontend/sram.py → misoc/liteethmini/mac/frontend/sram.py b/misoc/com/liteethmini/mac/frontend/sram.py → misoc/liteethmini/mac/frontend/sram.py
diff --git a/.../com/liteethmini/mac/frontend/wishbone.py → misoc/liteethmini/mac/frontend/wishbone.py b/.../com/liteethmini/mac/frontend/wishbone.py → misoc/liteethmini/mac/frontend/wishbone.py
diff --git a/misoc/com/liteethmini/phy/__init__.py → misoc/liteethmini/phy/__init__.py b/misoc/com/liteethmini/phy/__init__.py → misoc/liteethmini/phy/__init__.py
diff --git a/misoc/com/liteethmini/phy/gmii.py → misoc/liteethmini/phy/gmii.py b/misoc/com/liteethmini/phy/gmii.py → misoc/liteethmini/phy/gmii.py
diff --git a/misoc/com/liteethmini/phy/gmii_mii.py → misoc/liteethmini/phy/gmii_mii.py b/misoc/com/liteethmini/phy/gmii_mii.py → misoc/liteethmini/phy/gmii_mii.py
diff --git a/misoc/com/liteethmini/phy/loopback.py → misoc/liteethmini/phy/loopback.py b/misoc/com/liteethmini/phy/loopback.py → misoc/liteethmini/phy/loopback.py
diff --git a/misoc/com/liteethmini/phy/mii.py → misoc/liteethmini/phy/mii.py b/misoc/com/liteethmini/phy/mii.py → misoc/liteethmini/phy/mii.py
diff --git a/misoc/com/liteethmini/phy/s6rgmii.py → misoc/liteethmini/phy/s6rgmii.py b/misoc/com/liteethmini/phy/s6rgmii.py → misoc/liteethmini/phy/s6rgmii.py
diff --git a/misoc/com/liteethmini/phy/sim.py → misoc/liteethmini/phy/sim.py b/misoc/com/liteethmini/phy/sim.py → misoc/liteethmini/phy/sim.py
diff --git a/misoc/cpu/lm32.py → misoc/lm32/core.py b/misoc/cpu/lm32.py → misoc/lm32/core.py
diff --git a/extcores/lm32/lm32_config.v → misoc/lm32/verilog/lm32_config.v b/extcores/lm32/lm32_config.v → misoc/lm32/verilog/lm32_config.v
diff --git a/misoc/mem/__init__.py b/misoc/mem/__init__.py
diff --git a/misoc/mem/flash/__init__.py b/misoc/mem/flash/__init__.py
diff --git a/misoc/com/liteethmini/__init__.py → misoc/mor1kx/__init__.py b/misoc/com/liteethmini/__init__.py → misoc/mor1kx/__init__.py
diff --git a/misoc/cpu/mor1kx.py → misoc/mor1kx/core.py b/misoc/cpu/mor1kx.py → misoc/mor1kx/core.py
diff --git a/misoc/mem/flash/norflash16.py → misoc/norflash16.py b/misoc/mem/flash/norflash16.py → misoc/norflash16.py
diff --git a/misoc/spi/__init__.py b/misoc/spi/__init__.py
@@ -0,0 +1 @@
+from misoc.spi.core import SPIMaster
diff --git a/misoc/com/spi/__init__.py → misoc/spi/core.py b/misoc/com/spi/__init__.py → misoc/spi/core.py
@@ -17,7 +17,7 @@ def __init__(self, pads, width=24, div=2, cpha=1):
 
         self.irq = Signal()
 
-    ###
+        ###
 
         # ctrl
         start = Signal()
@@ -33,7 +33,6 @@ def __init__(self, pads, width=24, div=2, cpha=1):
 
         # clk
         i = Signal(max=div)
-        clk_en = Signal()
         set_clk = Signal()
         clr_clk = Signal()
         self.sync += [
@@ -124,7 +123,6 @@ def __init__(self, pads, width=24, div=2, cpha=1):
 
         # mosi
         if hasattr(pads, "mosi"):
-            mosi = Signal()
             sr_mosi = Signal(width)
 
             # (cpha = 1: propagated on clk rising edge)

diff --git a/misoc/com/spi/test/spi_master_tb.py → misoc/spi/test.py b/misoc/com/spi/test/spi_master_tb.py → misoc/spi/test.py
diff --git a/misoc/mem/flash/spiflash.py → misoc/spiflash.py b/misoc/mem/flash/spiflash.py → misoc/spiflash.py
diff --git a/misoc/cpu/timer.py → misoc/timer.py b/misoc/cpu/timer.py → misoc/timer.py
diff --git a/misoc/tools/__init__.py b/misoc/tools/__init__.py
diff --git a/misoc/tools/wishbone.py b/misoc/tools/wishbone.py
diff --git a/misoc/uart/__init__.py b/misoc/uart/__init__.py
@@ -0,0 +1 @@
+from misoc.uart.core import UART, RS232PHY
diff --git a/misoc/com/uart/phy/serial.py → misoc/uart/core.py b/misoc/com/uart/phy/serial.py → misoc/uart/core.py
@@ -1,13 +1,16 @@
 from migen import *
-from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
-from migen.flow.actor import Sink, Source
+from migen.bank.eventmanager import *
+from migen.genlib.record import Record
+from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
 
 
-class UARTPHYSerialRX(Module):
+class RS232PHYRX(Module):
     def __init__(self, pads, tuning_word):
         self.source = Source([("data", 8)])
+
         ###
+
         uart_clk_rxen = Signal()
         phase_accumulator_rx = Signal(32)
 
@@ -54,10 +57,12 @@ def __init__(self, pads, tuning_word):
                 )
 
 
-class UARTPHYSerialTX(Module):
+class RS232PHYTX(Module):
     def __init__(self, pads, tuning_word):
         self.sink = Sink([("data", 8)])
-        ###
+
+        # # #
+
         uart_clk_txen = Signal()
         phase_accumulator_tx = Signal(32)
 
@@ -96,9 +101,60 @@ def __init__(self, pads, tuning_word):
         ]
 
 
-class UARTPHYSerial(Module, AutoCSR):
+class RS232PHY(Module, AutoCSR):
     def __init__(self, pads, clk_freq, baudrate=115200):
         self._tuning_word = CSRStorage(32, reset=int((baudrate/clk_freq)*2**32))
-        self.submodules.tx = UARTPHYSerialTX(pads, self._tuning_word.storage)
-        self.submodules.rx = UARTPHYSerialRX(pads, self._tuning_word.storage)
+        self.submodules.tx = RS232PHYTX(pads, self._tuning_word.storage)
+        self.submodules.rx = RS232PHYRX(pads, self._tuning_word.storage)
         self.sink, self.source = self.tx.sink, self.rx.source
+
+
+def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
+    if sink_cd != source_cd:
+        fifo = AsyncFIFO([("data", 8)], depth)
+        return ClockDomainsRenamer({"write": sink_cd, "read": source_cd})(fifo)
+    else:
+        return SyncFIFO([("data", 8)], depth)
+
+
+class UART(Module, AutoCSR):
+    def __init__(self, phy,
+                 tx_fifo_depth=16,
+                 rx_fifo_depth=16,
+                 phy_cd="sys"):
+        self._rxtx = CSR(8)
+        self._txfull = CSRStatus()
+        self._rxempty = CSRStatus()
+
+        self.submodules.ev = EventManager()
+        self.ev.tx = EventSourceProcess()
+        self.ev.rx = EventSourceProcess()
+        self.ev.finalize()
+
+        # # #
+
+        # TX
+        tx_fifo = _get_uart_fifo(tx_fifo_depth, source_cd=phy_cd)
+        self.submodules += tx_fifo
+
+        self.comb += [
+            tx_fifo.sink.stb.eq(self._rxtx.re),
+            tx_fifo.sink.data.eq(self._rxtx.r),
+            self._txfull.status.eq(~tx_fifo.sink.ack),
+            Record.connect(tx_fifo.source, phy.sink),
+            # Generate TX IRQ when tx_fifo becomes non-full
+            self.ev.tx.trigger.eq(~tx_fifo.sink.ack)
+        ]
+
+        # RX
+        rx_fifo = _get_uart_fifo(rx_fifo_depth, sink_cd=phy_cd)
+        self.submodules += rx_fifo
+
+        self.comb += [
+            Record.connect(phy.source, rx_fifo.sink),
+            self._rxempty.status.eq(~rx_fifo.source.stb),
+            self._rxtx.w.eq(rx_fifo.source.data),
+            rx_fifo.source.ack.eq(self.ev.rx.clear),
+            # Generate RX IRQ when tx_fifo becomes non-empty
+            self.ev.rx.trigger.eq(~rx_fifo.source.stb)
+        ]
diff --git a/misoc/com/uart/test/test_serial_phy.py → misoc/uart/test.py b/misoc/com/uart/test/test_serial_phy.py → misoc/uart/test.py
diff --git a/misoc/video/__init__.py b/misoc/video/__init__.py
diff --git a/setup.py b/setup.py
@@ -5,10 +5,9 @@
 from setuptools import find_packages
 
 
-required_version = (3, 3)
-if sys.version_info < required_version:
-    raise SystemExit("MiSoC requires python {0} or greater".format(
-        ".".join(map(str, required_version))))
+if sys.version_info[:3] < (3, 3):
+    raise SystemExit("You need Python 3.3+")
+
 
 setup(
     name="misoc",
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1,2 @@
		from misoc.integration.soc_core import SoCCore
		from misoc.integration.soc_sdram import SoCSDRAM