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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 820ff2da2c69
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  • 4 commits
  • 43 files changed
  • 1 contributor

Commits on Jul 11, 2015

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    0e92cfe View commit details

Commits on Jul 13, 2015

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    8b02b58 View commit details
  2. refactor ddb/pdb/rdb

    sbourdeauducq committed Jul 13, 2015
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Showing with 686 additions and 814 deletions.
  1. +4 −2 artiq/coredevice/comm_dummy.py
  2. +4 −5 artiq/coredevice/comm_serial.py
  3. +4 −5 artiq/coredevice/comm_tcp.py
  4. +5 −7 artiq/coredevice/core.py
  5. +8 −13 artiq/coredevice/dds.py
  6. +12 −16 artiq/coredevice/ttl.py
  7. +8 −14 artiq/devices/pdq2/mediator.py
  8. +10 −15 artiq/devices/pxi6733/mediator.py
  9. +4 −5 artiq/frontend/artiq_compile.py
  10. +2 −0 artiq/frontend/artiq_gui.py
  11. +7 −8 artiq/frontend/artiq_master.py
  12. +20 −36 artiq/frontend/artiq_run.py
  13. +4 −5 artiq/language/__init__.py
  14. +0 −133 artiq/language/db.py
  15. +182 −0 artiq/language/environment.py
  16. +0 −54 artiq/language/experiment.py
  17. +2 −3 artiq/master/repository.py
  18. +0 −103 artiq/master/results.py
  19. +99 −65 artiq/master/worker_db.py
  20. +14 −18 artiq/master/worker_impl.py
  21. +1 −1 artiq/protocols/file_db.py
  22. +20 −19 artiq/protocols/sync_struct.py
  23. +14 −16 artiq/sim/devices.py
  24. +85 −79 artiq/test/coredevice.py
  25. +30 −32 artiq/test/coredevice_vs_host.py
  26. +9 −9 artiq/test/hardware_testbench.py
  27. +11 −5 artiq/test/scheduler.py
  28. +3 −1 artiq/test/transforms.py
  29. +9 −3 artiq/test/worker.py
  30. +1 −1 artiq/tools.py
  31. +1 −1 doc/manual/conf.py
  32. +3 −3 doc/manual/core_language_reference.rst
  33. +1 −1 doc/manual/developing_a_ndsp.rst
  34. +4 −15 doc/manual/faq.rst
  35. +21 −21 doc/manual/getting_started.rst
  36. +11 −11 examples/master/repository/dds_test.py
  37. +12 −16 examples/master/repository/flopping_f_simulation.py
  38. +4 −4 examples/master/repository/handover.py
  39. +3 −3 examples/master/repository/mandelbrot.py
  40. +16 −22 examples/master/repository/photon_histogram.py
  41. +14 −15 examples/master/repository/transport.py
  42. +12 −12 examples/sim/al_spectroscopy.py
  43. +12 −17 examples/sim/simple_simulation.py
6 changes: 4 additions & 2 deletions artiq/coredevice/comm_dummy.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
from operator import itemgetter

from artiq.language.db import AutoDB
from artiq.language.units import ms
from artiq.coredevice.runtime import LinkInterface

@@ -13,7 +12,10 @@ def emit_object(self):
return str(self.llvm_module)


class Comm(AutoDB):
class Comm:
def __init__(self, dmgr):
pass

def get_runtime_env(self):
return _RuntimeEnvironment()

9 changes: 4 additions & 5 deletions artiq/coredevice/comm_serial.py
Original file line number Diff line number Diff line change
@@ -3,16 +3,15 @@
import struct

from artiq.coredevice.comm_generic import CommGeneric
from artiq.language.db import *


logger = logging.getLogger(__name__)


class Comm(CommGeneric, AutoDB):
class DBKeys:
serial_dev = Argument()
baud_rate = Argument(115200)
class Comm(CommGeneric):
def __init__(self, dmgr, serial_dev, baud_rate=115200):
self.serial_dev = serial_dev
self.baud_rate = baud_rate

def open(self):
if hasattr(self, "port"):
9 changes: 4 additions & 5 deletions artiq/coredevice/comm_tcp.py
Original file line number Diff line number Diff line change
@@ -2,16 +2,15 @@
import socket

from artiq.coredevice.comm_generic import CommGeneric
from artiq.language.db import *


logger = logging.getLogger(__name__)


class Comm(CommGeneric, AutoDB):
class DBKeys:
host = Argument()
port = Argument(1381)
class Comm(CommGeneric):
def __init__(self, dmgr, host, port=1381):
self.host = host
self.port = port

def open(self):
if hasattr(self, "socket"):
12 changes: 5 additions & 7 deletions artiq/coredevice/core.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
import os

from artiq.language.core import *
from artiq.language.db import *
from artiq.language.units import ns

from artiq.transforms.inline import inline
@@ -46,13 +45,12 @@ def _no_debug_unparse(label, node):
pass


class Core(AutoDB):
class DBKeys:
comm = Device()
ref_period = Argument(8*ns)
external_clock = Argument(False)
class Core:
def __init__(self, dmgr, ref_period=8*ns, external_clock=False):
self.comm = dmgr.get("comm")
self.ref_period = ref_period
self.external_clock = external_clock

def build(self):
self.first_run = True
self.core = self
self.comm.core = self
21 changes: 8 additions & 13 deletions artiq/coredevice/dds.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,4 @@
from artiq.language.core import *
from artiq.language.db import *
from artiq.language.units import *


@@ -23,14 +22,12 @@ def __exit__(self, type, value, traceback):
self.dds_bus.batch_exit()


class DDSBus(AutoDB):
class DDSBus:
"""Core device Direct Digital Synthesis (DDS) bus batching driver.
Manages batching of DDS commands on a DDS shared bus."""
class DBKeys:
core = Device()

def build(self):
def __init__(self, dmgr):
self.core = dmgr.get("core")
self.batch = _BatchContextManager(self)

@kernel
@@ -46,7 +43,7 @@ def batch_exit(self):
syscall("dds_batch_exit")


class _DDSGeneric(AutoDB):
class _DDSGeneric:
"""Core device Direct Digital Synthesis (DDS) driver.
Controls one DDS channel managed directly by the core device's runtime.
@@ -57,12 +54,10 @@ class _DDSGeneric(AutoDB):
:param sysclk: DDS system frequency.
:param channel: channel number of the DDS device to control.
"""
class DBKeys:
core = Device()
sysclk = Argument()
channel = Argument()

def build(self):
def __init__(self, dmgr, sysclk, channel):
self.core = dmgr.get("core")
self.sysclk = sysclk
self.channel = channel
self.phase_mode = PHASE_MODE_CONTINUOUS

@portable
28 changes: 12 additions & 16 deletions artiq/coredevice/ttl.py
Original file line number Diff line number Diff line change
@@ -1,21 +1,18 @@
from artiq.language.core import *
from artiq.language.db import *


class TTLOut(AutoDB):
class TTLOut:
"""RTIO TTL output driver.
This should be used with output-only channels.
:param core: core device
:param channel: channel number
"""
class DBKeys:
core = Device()
channel = Argument()
def __init__(self, dmgr, channel):
self.core = dmgr.get("core")
self.channel = channel


def build(self):
# in RTIO cycles
self.o_previous_timestamp = int64(0)

@@ -58,7 +55,7 @@ def pulse(self, duration):
self.off()


class TTLInOut(AutoDB):
class TTLInOut:
"""RTIO TTL input/output driver.
In output mode, provides functions to set the logic level on the signal.
@@ -76,11 +73,10 @@ class TTLInOut(AutoDB):
:param core: core device
:param channel: channel number
"""
class DBKeys:
core = Device()
channel = Argument()
def __init__(self, dmgr, channel):
self.core = dmgr.get("core")
self.channel = channel

def build(self):
# in RTIO cycles
self.o_previous_timestamp = int64(0)
self.i_previous_timestamp = int64(0)
@@ -208,7 +204,7 @@ def timestamp(self):
return syscall("ttl_get", self.channel, self.i_previous_timestamp)


class TTLClockGen(AutoDB):
class TTLClockGen:
"""RTIO TTL clock generator driver.
This should be used with TTL channels that have a clock generator
@@ -217,9 +213,9 @@ class TTLClockGen(AutoDB):
:param core: core device
:param channel: channel number
"""
class DBKeys:
core = Device()
channel = Argument()
def __init__(self, dmgr, channel):
self.core = dmgr.get("core")
self.channel = channel

def build(self):
# in RTIO cycles
22 changes: 8 additions & 14 deletions artiq/devices/pdq2/mediator.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,4 @@
from artiq.language.core import *
from artiq.language.db import *
from artiq.language.units import *


@@ -154,19 +153,14 @@ def advance(self):
self.pdq.next_segment = -1


class CompoundPDQ2(AutoDB):
class DBKeys:
core = Device()
pdq2_devices = Argument()
trigger_device = Argument()
frame_devices = Argument()

def build(self):
self.pdq2s = [self.dbh.get_device(d) for d in self.pdq2_devices]
self.trigger = self.dbh.get_device(self.trigger_device)
self.frame0 = self.dbh.get_device(self.frame_devices[0])
self.frame1 = self.dbh.get_device(self.frame_devices[1])
self.frame2 = self.dbh.get_device(self.frame_devices[2])
class CompoundPDQ2:
def __init__(self, dmgr, pdq2_devices, trigger_device, frame_devices):
self.core = dmgr.get("core")
self.pdq2s = [dmgr.get(d) for d in self.pdq2_devices]
self.trigger = dmgr.get(trigger_device)
self.frame0 = dmgr.get(frame_devices[0])
self.frame1 = dmgr.get(frame_devices[1])
self.frame2 = dmgr.get(frame_devices[2])

self.frames = []
self.current_frame = -1
25 changes: 10 additions & 15 deletions artiq/devices/pxi6733/mediator.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
import numpy as np

from artiq.language.core import *
from artiq.language.db import *
from artiq.language.units import *
from artiq.wavesynth.compute_samples import Synthesizer

@@ -139,20 +138,16 @@ def advance(self):
self.daqmx.next_segment = -1


class CompoundDAQmx(AutoDB):
class DBKeys:
core = Device()
daqmx_device = Argument()
clock_device = Argument()
channel_count = Argument()
sample_rate = Argument()
sample_rate_in_mu = Argument(False)

def build(self):
self.daqmx = self.dbh.get_device(self.daqmx_device)
self.clock = self.dbh.get_device(self.clock_device)

if not self.sample_rate_in_mu:
class CompoundDAQmx:
def __init__(self, dmgr, daqmx_device, clock_device, channel_count,
sample_rate, sample_rate_in_mu=False):
self.core = dmgr.get("core")
self.daqmx = dmgr.get(daqmx_device)
self.clock = dmgr.get(clock_device)
self.channel_count = channel_count
if self.sample_rate_in_mu:
self.sample_rate = sample_rate
else:
self.sample_rate = self.clock.frequency_to_ftw(sample_rate)

self.frame = None
9 changes: 4 additions & 5 deletions artiq/frontend/artiq_compile.py
Original file line number Diff line number Diff line change
@@ -4,7 +4,7 @@
import argparse

from artiq.protocols.file_db import FlatFileDB
from artiq.master.worker_db import DBHub
from artiq.master.worker_db import DeviceManager
from artiq.tools import *


@@ -36,15 +36,14 @@ def main():
args = get_argparser().parse_args()
init_logger(args)

ddb = FlatFileDB(args.ddb)
dmgr = DeviceManager(FlatFileDB(args.ddb))
pdb = FlatFileDB(args.pdb)
dbh = DBHub(ddb, pdb, rdb=None, read_only=True)

try:
module = file_import(args.file)
exp = get_experiment(module, args.experiment)
arguments = parse_arguments(args.arguments)
exp_inst = exp(dbh, **arguments)
exp_inst = exp(dmgr, pdb, **arguments)

if (not hasattr(exp.run, "k_function_info")
or not exp.run.k_function_info):
@@ -56,7 +55,7 @@ def main():
[exp_inst], {},
with_attr_writeback=False)
finally:
dbh.close_devices()
dmgr.close_devices()

if rpc_map:
raise ValueError("Experiment must not use RPC")
2 changes: 2 additions & 0 deletions artiq/frontend/artiq_gui.py
Original file line number Diff line number Diff line change
@@ -18,9 +18,11 @@
from artiq.gui.schedule import ScheduleDock
from artiq.gui.log import LogDock


data_dir = os.path.join(os.path.abspath(os.path.dirname(__file__)),
"..", "gui")


def get_argparser():
parser = argparse.ArgumentParser(description="ARTIQ GUI client")
parser.add_argument(
15 changes: 7 additions & 8 deletions artiq/frontend/artiq_master.py
Original file line number Diff line number Diff line change
@@ -6,10 +6,10 @@
import os

from artiq.protocols.pc_rpc import Server
from artiq.protocols.sync_struct import Publisher
from artiq.protocols.sync_struct import Notifier, Publisher, process_mod
from artiq.protocols.file_db import FlatFileDB
from artiq.master.scheduler import Scheduler
from artiq.master.results import RTResults, get_last_rid
from artiq.master.worker_db import get_last_rid
from artiq.master.repository import Repository
from artiq.tools import verbosity_args, init_logger

@@ -36,7 +36,7 @@ def main():
init_logger(args)
ddb = FlatFileDB("ddb.pyon")
pdb = FlatFileDB("pdb.pyon")
rtr = RTResults()
rtr = Notifier(dict())
repository = Repository()

if os.name == "nt":
@@ -47,11 +47,10 @@ def main():
atexit.register(lambda: loop.close())

worker_handlers = {
"req_device": ddb.request,
"req_parameter": pdb.request,
"get_device": ddb.get,
"get_parameter": pdb.get,
"set_parameter": pdb.set,
"init_rt_results": rtr.init,
"update_rt_results": rtr.update,
"update_rt_results": lambda mod: process_mod(rtr, mod),
}
scheduler = Scheduler(get_last_rid() + 1, worker_handlers)
worker_handlers["scheduler_submit"] = scheduler.submit
@@ -72,7 +71,7 @@ def main():
"schedule": scheduler.notifier,
"devices": ddb.data,
"parameters": pdb.data,
"rt_results": rtr.groups,
"rt_results": rtr,
"explist": repository.explist
})
loop.run_until_complete(server_notify.start(
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