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misoclib/video/dvisampler: add fifo_depth parameter
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enjoy-digital committed Jul 13, 2015
1 parent e6da1d1 commit 4dca66b
Showing 2 changed files with 4 additions and 4 deletions.
4 changes: 2 additions & 2 deletions misoclib/video/dvisampler/__init__.py
Original file line number Diff line number Diff line change
@@ -13,7 +13,7 @@


class DVISampler(Module, AutoCSR):
def __init__(self, pads, lasmim, n_dma_slots=2):
def __init__(self, pads, lasmim, n_dma_slots=2, fifo_depth=512):
self.submodules.edid = EDID(pads)
self.submodules.clocking = Clocking(pads)

@@ -63,7 +63,7 @@ def __init__(self, pads, lasmim, n_dma_slots=2):
self.resdetection.vsync.eq(self.syncpol.vsync)
]

self.submodules.frame = FrameExtraction(24*lasmim.dw//32)
self.submodules.frame = FrameExtraction(24*lasmim.dw//32, fifo_depth)
self.comb += [
self.frame.valid_i.eq(self.syncpol.valid_o),
self.frame.de.eq(self.syncpol.de),
4 changes: 2 additions & 2 deletions misoclib/video/dvisampler/analysis.py
Original file line number Diff line number Diff line change
@@ -109,7 +109,7 @@ def __init__(self, nbits=11):


class FrameExtraction(Module, AutoCSR):
def __init__(self, word_width):
def __init__(self, word_width, fifo_depth):
# in pix clock domain
self.valid_i = Signal()
self.vsync = Signal()
@@ -155,7 +155,7 @@ def __init__(self, word_width):
]

# FIFO
fifo = RenameClockDomains(AsyncFIFO(word_layout, 512),
fifo = RenameClockDomains(AsyncFIFO(word_layout, fifo_depth),
{"write": "pix", "read": "sys"})
self.submodules += fifo
self.comb += [

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