Making the Opsis board work

 * edid-decode changed from b2da151 to 5eeb151
    * 5eeb151 - edid-decode: replace AdobeYCC/RGB by opYCC/RGB <Hans Verkuil>

 * litedram changed from 7a5ac75 to ea1ac4d
    * ea1ac4d - s6ddrphy: Pass missing nranks parameter. <Tim 'mithro' Ansell>
    * e5696ad - frontend/ecc: add enable csr <Florent Kermarrec>
    * e6ef89a - frontend/axi: optimize burst2beat timings <Florent Kermarrec>
    * 6941285 - frontend/ecc: split Write/Read path and add buffer to improve timings <Florent Kermarrec>
    * 041817d - frontend/ecc: use csr instead of signal for control <Florent Kermarrec>
    * b145b0c - frontend/axi: fix write response implementation <Florent Kermarrec>
    * d23dbf6 - phy: add nranks to all phys <Florent Kermarrec>
    * 461b076 - frontend/ecc: add ecc adapter <Florent Kermarrec>
    * c84b587 - frontend: add initial ecc code (still need to be integrated) <Florent Kermarrec>
    * a8d2672 - phy/s7ddrphy_halfrate_bl8: don't generate dqs pre/post-amble, needs simulation <Florent Kermarrec>
    * 5719d71 - phy/s7ddrphy_halfrate_bl8: fix cs_n <Florent Kermarrec>
    * 36fa324 - core/multiplexer: fix regression (introduced by multirank support) <Florent Kermarrec>
    * 42d0e5b - core/multiplexer: add more information on odt fixme <Florent Kermarrec>
    * 919b756 - phy/model: pass nranks to Interface <Florent Kermarrec>
    * f5c7b61 - multirank: set default nranks to 1 if not specified <Florent Kermarrec>
    * f3d403f - s7ddrphy: fix typo (reset_n --> cs_n) <Florent Kermarrec>
    * 37f1dec - multirank: one cs_n/cke/odt/clk per rank <Florent Kermarrec>
    * 3e17d18 - phy: add halfrate_bl8 variant for s7ddrphy <Florent Kermarrec>
    *   412e9a5 - Merge pull request #38 from enjoy-digital/multirank <enjoy-digital>
    |\
    | * 8ddc6c7 - drive odt of all ranks, fixes and test non regression with 1 rank <Florent Kermarrec>
    | * d4f434d - dfii: send command to all ranks <Florent Kermarrec>
    | * b1c2739 - initial multirank support (nbankmachines = nranks * (2**bankbits)) <Florent Kermarrec>
    * |   d9c2430 - Merge pull request #36 from JohnSully/timing_1 <enjoy-digital>
    |\ \
    | |/
    |/|
    | * efd7a47 - Fix failing timing <>
    * | cc481be - examples: add sdram_rank_nb and user_ports_id_width <Florent Kermarrec>
    |/
    * 849b1f6 - frontend/axi: generate rlast signal <Florent Kermarrec>
    * 1fa73e4 - test: update <Florent Kermarrec>
    * 7b61b68 - sdram_init: min value for wr is 5 <Florent Kermarrec>
    * 1652ab9 - examples/litedram_gen: fix address width of axi ports (addressing in bytes not words) <Florent Kermarrec>
    * 1e64b7f - examples/litedram_gen: expose resp signals to user <Florent Kermarrec>
    * 700f76c - frontend/axi: add resp signals <Florent Kermarrec>
    * 47fed1b - frontend/axi: add last limitation <Florent Kermarrec>
    * de69867 - examples/litedram_gen: expose last signals to user <Florent Kermarrec>
    * e8bd782 - examples/litedram_gen: expose burst signals to user <Florent Kermarrec>
    * e1598ce - phy/s7ddrphy: fix BL8 assert <Florent Kermarrec>
    * ebba39d - README: update <Florent Kermarrec>
    * e528e92 - phy/s7ddrphy: add assertion to avoid generating 1:2 controller with DDR3 (needs BL8 support in the PHY) <Florent Kermarrec>
    * 6017e7a - phy/s7ddrphy: fix dqs_sys_latency for DDR2 <Florent Kermarrec>
    * 7b42739 - phy/s7ddrphy: simplify cmd/dat phases computation and remove restrictions. <Florent Kermarrec>
    * 6148618 - phy/s7ddrphy: use dict in get_cl_cw function <Florent Kermarrec>
    * 5e4dca9 - add examples with standalone cores for arty and genesys2 <Florent Kermarrec>
    * dce4ede - README: update <Florent Kermarrec>
    * f6797a1 - test/test_axi: add burst wrap test and fix code <Florent Kermarrec>
    * 47988d8 - frontend/axi: remove alignment limitation since we are in fact supporting unaligned transfers as described in the specification. <Florent Kermarrec>
    * 6cc42c6 - frontend/axi: add wrap burst support <Florent Kermarrec>
    * 9c729ae - core: replace adr with addr on native interface (closer to AXI and allow some simplifications) <Florent Kermarrec>
    * 0506708 - core/controller: remove simulation workaround <Florent Kermarrec>
    * bc8a9ce - README: update <Florent Kermarrec>
    * 6f7ae84 - frontend/axi: increase default depth of buffers to improve performance <Florent Kermarrec>
    * ed7eef1 - phy/s7ddrphy: fix preamble/posamble latency when with_odelay (-1 since dqs clk is not shifted) <Florent Kermarrec>
    * c37d3af - frontend/bist: only keep random datas (we can generate random addresses with control) <Florent Kermarrec>
    * b1e734b - frontend/bist: only use cdc on registers if needed (ie not in sys clock domain) <Florent Kermarrec>
    * 92c8513 - frontend/axi: add buffer to accept command before converting burst to beats <Florent Kermarrec>
    * c15c474 - test/test_axi: split reads/writes generators <Florent Kermarrec>
    * 95cb7cd - test: rename read/write generators to handlers <Florent Kermarrec>
    * d5d6737 - frontend/axi: fix read id <Florent Kermarrec>
    * 10229d1 - test/test_axi: improve test_axi2native <Florent Kermarrec>
    * 295f016 - frontend/axi: add features/limitations <Florent Kermarrec>
    * 6a46ea3 - test/test_bist: add generator test, remove async test <Florent Kermarrec>
    * 7677a85 - core/bankmachine: expose cmd_buffer_buffered param and small cleanup <Florent Kermarrec>

 * liteeth changed from 24b0d2b to 3d86844
    * 3d86844 - core/mac/sram: fix code refactoring <Florent Kermarrec>
    * 5106bcd - core/mac/sram: simplify last_be code <Florent Kermarrec>
    * ce72e34 - core/mac: pass endianness and use if for last_be gen/check <Florent Kermarrec>
    * 94af3d6 - README: update and rename example_designs to examples <Florent Kermarrec>

 * litepcie changed from a97a691 to 3e8de2d
    * 3e8de2d - phy/s7pciephy: remove clock constraints from phy <Florent Kermarrec>
    * 6f2d97a - README: update and rename example_designs to example <Florent Kermarrec>

 * litesata changed from 002cd25 to fb72044
    * fb72044 - README: update and rename example_designs to examples <Florent Kermarrec>

 * litescope changed from f26e36e to 686db4f
    *   686db4f - Merge pull request #12 from xobs/default-length <enjoy-digital>
    |\
    | * 4f8b9a3 - analyzer-driver: use default depth from config <Sean Cross>
    |/
    * 7c1c62e - README: update and rename example_designs to examples <Florent Kermarrec>
    * 3567b68 - dump/vcd: fix code generation <Florent Kermarrec>
    * 182b683 - core: change cd parameter to clock_domain (keep retro compatibility for now) <Florent Kermarrec>

 * liteusb changed from e841c56 to 0a9110f
    * 0a9110f - README: update and rename example_designs to examples <Florent Kermarrec>

 * litevideo changed from 7b4240f to 13d85a1
    * 13d85a1 - README: update <Florent Kermarrec>

 * litex changed from 7a14b75c to 537b0e90
    *   537b0e90 - Merge pull request #101 from cr1901/icestorm-migen-pull <enjoy-digital>
    |\
    | * 5c83c881 - Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run. <William D. Jones>
    * | 9c6f76f1 - bios/sdram: mode sdhw() <Florent Kermarrec>
    * | a44bedd5 - bios/sdram: add missing #ifdef <Florent Kermarrec>
    * | 0e68daeb - targets: self.pll_sys --> pll_sys <Florent Kermarrec>
    * | 1468b9f3 - bios/sdram: show all read scans when failing. <Florent Kermarrec>
    * | 07e4c183 - cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise) <Florent Kermarrec>
    * | df3f003e - soc_sdram: update with litedram <Florent Kermarrec>
    |/
    *   bebc667d - Merge pull request #99 from cr1901/mk-copy-main-ram <enjoy-digital>
    |\
    | * bd70ba27 - Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without main_ram region. <William D. Jones>
    * |   69716852 - Merge pull request #100 from cr1901/tinyprog-fix <enjoy-digital>
    |\ \
    | * | c812321a - lattice/programmer: Use --program-image option with tinyprog if address is given. <William D. Jones>
    | |/
    * | 12a89447 - soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...) <Florent Kermarrec>
    * | 2b786065 - targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen <Florent Kermarrec>
    * | 26963d62 - libnet/microudp: (WIP) fix endianness issues <Jean-François Nguyen>
    * |   d9d0320d - Merge pull request #98 from jfng/fix_typo <enjoy-digital>
    |\ \
    | * | 22c01313 - fix typo and unused include <Jean-François Nguyen>
    |/ /
    * | fb24ac0e - cpu/minerva: add workaround on import until code is released <Florent Kermarrec>
    * | 9cfae4df - setup.py: create litex_sim exec to ease simulation <Florent Kermarrec>
    * | 8f377307 - add Minerva support <Jean-François Nguyen>
    * | 1944289e - litex_server: update pcie and remove bar_size parameter <Florent Kermarrec>
    |/
    *   c5a2d6f3 - Merge pull request #96 from cr1901/tinyfpga_bx <Tim Ansell>
    |\
    | * 29492624 - build/platforms: Add TinyFPGA BX board and programmer. <William D. Jones>
    * |   3cb754da - Merge pull request #95 from cr1901/lm32-lite <Tim Ansell>
    |\ \
    | * | ed507d61 - Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly. <William D. Jones>
    | |/
    * | 28cd2da2 - README: update <Florent Kermarrec>
    |/
    * 05c7b9da - Merge pull request #94 from cr1901/nextpnr <enjoy-digital>
    * 7af89efc - lattice/icestorm: Add nextpnr pnr as alternate pnr tool. <William D. Jones>

 * migen changed from 0.6.dev-162-ga6082d5 to 0.6.dev-168-gca0df1c
    * ca0df1c - build.platforms: add ice40_up5k_b_evn platform. <whitequark>
    * b2740d9 - build.lattice.icestorm: write build script even on dry run. <whitequark>
    * 2a7e33e - Emit `default_nettype none. <David Craven>
    * cff127d - build/platforms: Add TinyFPGA BX board and programmer. <William D. Jones>
    * 97e2651 - kasli: set USERID and USR_ACCESS <Robert Jördens>
    * 58894fb - lattice/icestorm: Add nextpnr as alternate pnr tool. (#124) <William D. Jones>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 ea1ac4d6d72ecb9a65fb884857db8ba6851f3230 litedram (heads/s6-rank-fix)
 3d868449e9c38a00524cff8ed2bf5dec2fc0d858 liteeth (remotes/origin/HEAD)
 3e8de2d1ef347a1fdfbd01601b1bbdc4558dd90a litepcie (remotes/origin/HEAD)
 fb72044dabd121b4643a936b21ca3bf3aed75499 litesata (remotes/origin/HEAD)
 686db4f3cd71bade8dd777d112e66797662f5bad litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 537b0e9058e6a5b77f434f46f3a56849c82064bd litex (remotes/origin/HEAD)
 ca0df1c148950213ff0551a8ec7c188a5910906e migen (0.6.dev-168-gca0df1c)

 * litedram changed from f36bcff to 30d9a3e
    * 30d9a3e - modules: add MT40A1G8 DDR4 <Florent Kermarrec>
    * 4459bd2 - frontend/axi: same condition to connect connect wdata.we and wdata <Florent Kermarrec>
    * d10e2e9 - core: make address_mapping a controller setting <Florent Kermarrec>
    * 7973b7d - frontend/axi: emits the write command only if we have the write data <Florent Kermarrec>
    * 6fa891d - frontend/axi: fix write response for bursts <Florent Kermarrec>
    * 93e8510 - test/test_axi: add bursts to axi2native <Florent Kermarrec>
    * e27fbc2 - test/test_axi: move definitions to top and make Access herit from Burst <Florent Kermarrec>
    * 4470f32 - test/test_axi: change order of the tests <Florent Kermarrec>
    * 070cc26 - test/test_axi: use separate generator for writes cmd/data <Florent Kermarrec>
    * 127e928 - frontend/wishbone: simplify LiteDRAMWishbone2Native code (resource usage almost the same) <Florent Kermarrec>
    * ca82ac1 - frontend/wishbone: add LiteDRAMWishbone2AXI <Florent Kermarrec>
    * 3586e15 - frontend/axi: improve len/size comment (-1), set default id_width to 1 <Florent Kermarrec>
    * 71be616 - frontend/axi: be sure wdata is available before sending the command to the controller <Florent Kermarrec>
    * 55b5f40 - modules: add AS4C256M16D3A <Florent Kermarrec>
    *   69ea866 - Merge pull request #62 from daveshah1/AS4C32M16 <enjoy-digital>
    |\
    | * 3a5d45b - modules: Add AS4C32M16 32Mx16 SDRAM <David Shah>
    * | b41fe61 - phy/kusddrphy/ddr4: multiplexed address bits are always the same (14, 15, 16) and fix ba/bg ordering <Florent Kermarrec>
    * | 2e19787 - phy/kusddrphy: add dfi mux on address/control signals <Florent Kermarrec>
    * | a8c3d39 - sdram_init: fix compilation <Florent Kermarrec>
    * | af34489 - common: add DDR4 burst_length <Florent Kermarrec>
    * | 2a9fb11 - phy/kusddrphy: more genericity, initial DDR4 support <Florent Kermarrec>
    * | ae5dc9f - sdram_init: add initial DDR4 initialization <Florent Kermarrec>
    * | 8181fea - modules: add EDY4016A DDR4 <Florent Kermarrec>
    * | 346e64c - frontend/ecc: fix typo <Florent Kermarrec>
    |/
    * 82c08c7 - phy/gensdrphy: use tristate input <Florent Kermarrec>
    * 9ce84d9 - modules: add MT48LC16M16 (ulx3s) <Florent Kermarrec>

 * liteeth changed from 40b99ec to 52c2301
    * 52c2301 - frontend/etherbone: reduce default buffer_depth to 4 <Florent Kermarrec>
    * 602ddec - common: use reverse_bytes from litex.gen <Florent Kermarrec>

 * litepcie changed from a8b8048 to 48f662e
    * 48f662e - phy/s7pciephy: force user to use register_pll1 if pll1 is needed <Florent Kermarrec>
    * 33f4601 - phy/s7pciephy: add register_pll1 method <Florent Kermarrec>
    * 80f28b1 - common: use reverse_bits/reverse_bytes from litex.gen <Florent Kermarrec>

 * litex changed from v0.1-532-g98159209 to v0.1-602-gbc173380
    *   bc173380 - Merge pull request timvideos#126 from mithro/toolchain-fix <Tim Ansell>
    |\
    | * b1425ba8 - lattice/icestorm: Add toolchain_path so it doesn't end up kwargs. <Tim 'mithro' Ansell>
    |/
    * af25bf2b - soc_core: check for cpu before checking interrupt <Florent Kermarrec>
    * b4bdf2a0 - cores/clock/S7: just reset the generated clock, not the PLL/MMCM <Florent Kermarrec>
    * 86fd945b - bios/main: fix typo on mor1kx <Florent Kermarrec>
    * af950285 - cpu/mor1kx: use clang only for linux variant <Florent Kermarrec>
    * 04523bc2 - xilinx/vivado: fix migen merge <Florent Kermarrec>
    * f3343c46 - platforms: remove versaecp55g_sdram <Florent Kermarrec>
    * 58414b18 - build/xilinx/vivado: merge migen change <Florent Kermarrec>
    * a7f17f99 - build: use default toolchain_path on all backend when passed value is None <Florent Kermarrec>
    * eed1d5cb - generic_platform: use set for sources <Florent Kermarrec>
    * 665fff83 - build: merge more migen changes <Florent Kermarrec>
    * 70f48775 - platforms/versa_ecp5: import migen changes <Florent Kermarrec>
    * 4ff241b9 - targets/ulx3s,versa_ecp5: prjtrellis toolchain renamed to trellis <Florent Kermarrec>
    * cb86728a - build/lattice: import changes from migen <Florent Kermarrec>
    * 8574c62f - targets/versa_ecp5: increase sys_clk_freq to 50MHz <Florent Kermarrec>
    * a752dafb - targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll <Florent Kermarrec>
    * 87c7d23d - targets/ulx3s: for now revert to 25MHz clock/no pll <Florent Kermarrec>
    * d1baae36 - platforms/versa_ecp5: add ecp5 soc hat ios <Florent Kermarrec>
    *   b3bf1c95 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   1be6762d - Merge pull request timvideos#125 from daveshah1/trellis_sdram <enjoy-digital>
    | |\
    | | * f08f80be - working on Versa-5G dram <David Shah>
    | | * d78d5d3e - Debugging ULX3S SDRAM <David Shah>
    * | | 425ad755 - plarforms: rename versa/versaecp55g to versa_ecp3/versa_ecp5 <Florent Kermarrec>
    |/ /
    * | c57aa545 - targets/ulx3s: get memtest working by disabling sdram refresh <Florent Kermarrec>
    * | 9a644717 - soc/integration/soc_sdram: allow using axi interface with litedram <Florent Kermarrec>
    * | 416bdb64 - boards/platforms: add avalanche polarfire board ios definition <Florent Kermarrec>
    * | fc0d5c39 - bios/sdram: iterate multiple time for write leveling and add vote to eliminate transcients <Florent Kermarrec>
    * | 09f962fd - target/kcu105: add reset button <Florent Kermarrec>
    * | 169f8d8c - boards/platforms/kcu105: fix sdram/dq pin swap <Florent Kermarrec>
    * | 2624ba48 - bios/sdram: replace DDR3_MR1 constant with DDRX_MR1 <Florent Kermarrec>
    * | 6be74aa1 - boards/targets: add kcu105 <Florent Kermarrec>
    * |   93c62325 - Merge pull request timvideos#122 from daveshah1/trellis_ulx3s <enjoy-digital>
    |\ \
    | |/
    | * 0729b3a0 - ulx3s: Connect SDRAM clock <David Shah>
    | * 84044349 - Fix Trellis build; ULX3S demo boots to BIOS <David Shah>
    | * 0c1d8d59 - trellis: Switch to using LPF for constraints <David Shah>
    * |   00ef8240 - Merge pull request timvideos#124 from jfng/master <enjoy-digital>
    |\ \
    | * | dcbe759b - build/sim/verilator: don't use --threads when $(THREADS) is unset <Jean-François Nguyen>
    |/ /
    * | 6f38213a - boards/platforms/kc705: add user_sma_mgt_refclk <Florent Kermarrec>
    * |   4cdd6799 - Merge pull request timvideos#123 from cr1901/prv32-min <enjoy-digital>
    |\ \
    | * | e56f7182 - libbase/crt0-picorv32: Emulate support for a relocatable IRQ vector (hardcoded at synthesis time). <William D. Jones>
    | * | f32121e0 - cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector. <William D. Jones>
    | * | 77389d27 - libbase/crt0-picorv32: Ensure BSS is cleared on boot. <William D. Jones>
    | * | f69bd877 - cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations). <William D. Jones>
    | * | d05fe673 - cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs. <William D. Jones>
    * | | f7969b66 - cores/clock: add with_reset parameter (default to True) <Florent Kermarrec>
    | |/
    |/|
    * | 445c4940 - boards/platforms/kcu105: add sfp_tx/rx definition <Florent Kermarrec>
    |/
    * e9d4c882 - build/lattice/prjtrellis: fix default toolchain_path <Florent Kermarrec>
    * 468780c0 - soc/cores/spi_flash: add endianness parameter <Florent Kermarrec>
    * 6f3131e2 - soc/interconnect/stream_packet: use reverse_bytes from litex.gen <Florent Kermarrec>
    * b7968538 - gen: add common with reverse_bits/reverse_bytes functions <Florent Kermarrec>
    * 71fc34d7 - boards/targets/ulx3s: reduce l2_size <Florent Kermarrec>
    * 75d073f3 - build/lattice/prjtrellis: fix typo <Florent Kermarrec>
    * 6048a529 - build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper, handle inouts. <Florent Kermarrec>
    * 2243f628 - build/lattice/common: fix LatticeECPXPrjTrellisTristateImpl <Florent Kermarrec>
    *   3a8bb94a - Merge pull request timvideos#121 from cr1901/patch-3 <Tim Ansell>
    |\
    | * f3111e11 - Update vivado.py <William D. Jones>
    |/
    * 98fa8996 - boards/targets: add ulx3s <Florent Kermarrec>
    * 7d779473 - boards/platforms: add ulx3s <Florent Kermarrec>
    * d9dcad33 - build/lattice/prjtrellis: add inout support <Florent Kermarrec>
    * 091ad799 - build/lattice/common: add tristate support <Florent Kermarrec>
    * 23acefb1 - boards/targets/versaecp55g_prjtrellis: simple.py example working, specific target no longer needed <Florent Kermarrec>
    * 1097f822 - build/lattice/prjtrellis: set default toolchain_path to "/opt/prjtrellis" <Florent Kermarrec>
    * 52917a71 - boards/targets/simple: add gateware-toolchain parameter <Florent Kermarrec>
    * d84083f6 - boards/platforms/versaecp55g: use ftdi serial pins <Florent Kermarrec>
    * c05b9ef2 - build/lattice/prjtrellis: test and fix iowrapper multi-bit signals support <Florent Kermarrec>
    * a8f819fe - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    * 4eb314a2 - boards/targets/versaecp55g: use new iowrapper support, basic led blink and ios working :) <Florent Kermarrec>
    * 27ec2a59 - build/lattice/prjtrellis: generate iowrapper to set constraints and TRELLIS_IO <Florent Kermarrec>
    * c506c975 - gen/fhdl/verilog: set direction to io signals <Florent Kermarrec>

 * migen changed from 0.6.dev-179-g657c0c7 to 0.6.dev-209-gc285c12
    * c285c12 - genlib/fsm: allow subclassing FSM and overriding control functionality. <whitequark>
    * dd78f38 - sim/core: fix typo breaking `yield x.part(...).eq(...)`. <whitequark>
    * f8bea17 - test/test_fsm: fix typo. <whitequark>
    * 319d3cd - build: use default toolchain_path on all backends when toolchain_path passed value is None <Florent Kermarrec>
    * e7c9ab0 - xilinx/vivado: fix missing **kwargs <Florent Kermarrec>
    * 8789575 - xilinx/vivado: fix edifs/ips import <Florent Kermarrec>
    * 5851076 - build: make sure build_name/kwargs are passed to platform.get_verilog on all backends <Florent Kermarrec>
    * ec40e98 - xilinx/vivado: enable xpm libraries <Florent Kermarrec>
    * 21bb0f7 - xilinx/vivado: add support for importing edifs for ips <Florent Kermarrec>
    * 263e729 - xilinx/programmer: add device parameter <Florent Kermarrec>
    * f71b4a8 - xilinx/ise: set build_name as top name <Florent Kermarrec>
    * 2dc085d - lattice/common: no need to differentiate nbits==1 and nbits > 1 <Florent Kermarrec>
    * 48023fa - lattice: fix Misc constraints <Florent Kermarrec>
    * 1fdf5db - lattice/diamond: use build_name as top name <Florent Kermarrec>
    * 28a5f32 - genlib/fsm: add basic FSM tests. <whitequark>
    * 9cd4e2c - remove asic_syntax and other cleanups <Sebastien Bourdeauducq>
    * cf4c3ef - build/lattice/diamond: translate `keep` and `no_retiming` attributes. <whitequark>
    * d5ac858 - build/lattice/diamond: save LDF project after creating it. <whitequark>
    * 2025071 - build/lattice/diamond: shorten pointlessly long paths. <whitequark>
    * 7303a8a - build/platforms/versaecp55g: add PCIe pins. <whitequark>
    * 0c5d42c - Add Project Trellis Backend (timvideos#156) <William D. Jones>
    * 37deff1 - build/platforms/versaecp55g: fix IOStandard for ext_clk. <whitequark>
    * c79d988 - build/platforms/versaecp55g: add X3 external connector. <whitequark>
    * d60cea0 - build/platforms/versaecp55g: add external clock input. <whitequark>
    * c51a064 - build/platforms/versaecp55g: allow programming without ispCLOCK in chain. <whitequark>
    * 34eeb3b - build/platforms/versaecp55g: import from litex. <whitequark>
    * 7bdc4ed - build/lattice/diamond: add Linux support. <whitequark>
    * 3a84a8b - build/lattice/diamond: only run Jedecgen for MachXO. <whitequark>
    * 966781b - class Tristate: add support for target parameter with oe, o and i subsignals. (timvideos#148) <Staf Verhaegen>
    * 907afd5 - platforms/icebreaker: Rename I/O w/ @esden's feedback. <William D. Jones>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 30d9a3e2c22459470605b8d46f27d339b47f7987 litedram (remotes/origin/HEAD)
 52c23015b052e40600a84ac73227fb5a0f0ce862 liteeth (remotes/origin/HEAD)
 48f662e3928aa5af25aef932a8b1744d1f29c260 litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 bc173380f21f82a82fc41e9face61b0c33e7f8e4 litex (v0.1-602-gbc173380)
 c285c12905cca3d8db59ce9fba3bbcd7e781e3c3 migen (0.6.dev-209-gc285c12)

 * litedram changed from f36bcff to 69ea866
    *   69ea866 - Merge pull request #62 from daveshah1/AS4C32M16 <enjoy-digital>
    |\
    | * 3a5d45b - modules: Add AS4C32M16 32Mx16 SDRAM <David Shah>
    * | b41fe61 - phy/kusddrphy/ddr4: multiplexed address bits are always the same (14, 15, 16) and fix ba/bg ordering <Florent Kermarrec>
    * | 2e19787 - phy/kusddrphy: add dfi mux on address/control signals <Florent Kermarrec>
    * | a8c3d39 - sdram_init: fix compilation <Florent Kermarrec>
    * | af34489 - common: add DDR4 burst_length <Florent Kermarrec>
    * | 2a9fb11 - phy/kusddrphy: more genericity, initial DDR4 support <Florent Kermarrec>
    * | ae5dc9f - sdram_init: add initial DDR4 initialization <Florent Kermarrec>
    * | 8181fea - modules: add EDY4016A DDR4 <Florent Kermarrec>
    * | 346e64c - frontend/ecc: fix typo <Florent Kermarrec>
    |/
    * 82c08c7 - phy/gensdrphy: use tristate input <Florent Kermarrec>
    * 9ce84d9 - modules: add MT48LC16M16 (ulx3s) <Florent Kermarrec>

 * liteeth changed from 40b99ec to 52c2301
    * 52c2301 - frontend/etherbone: reduce default buffer_depth to 4 <Florent Kermarrec>
    * 602ddec - common: use reverse_bytes from litex.gen <Florent Kermarrec>

 * litepcie changed from a8b8048 to 80f28b1
    * 80f28b1 - common: use reverse_bits/reverse_bytes from litex.gen <Florent Kermarrec>

 * litex changed from 98159209 to fc0d5c39
    * fc0d5c39 - bios/sdram: iterate multiple time for write leveling and add vote to eliminate transcients <Florent Kermarrec>
    * 09f962fd - target/kcu105: add reset button <Florent Kermarrec>
    * 169f8d8c - boards/platforms/kcu105: fix sdram/dq pin swap <Florent Kermarrec>
    * 2624ba48 - bios/sdram: replace DDR3_MR1 constant with DDRX_MR1 <Florent Kermarrec>
    * 6be74aa1 - boards/targets: add kcu105 <Florent Kermarrec>
    *   93c62325 - Merge pull request #122 from daveshah1/trellis_ulx3s <enjoy-digital>
    |\
    | * 0729b3a0 - ulx3s: Connect SDRAM clock <David Shah>
    | * 84044349 - Fix Trellis build; ULX3S demo boots to BIOS <David Shah>
    | * 0c1d8d59 - trellis: Switch to using LPF for constraints <David Shah>
    * |   00ef8240 - Merge pull request #124 from jfng/master <enjoy-digital>
    |\ \
    | * | dcbe759b - build/sim/verilator: don't use --threads when $(THREADS) is unset <Jean-François Nguyen>
    |/ /
    * | 6f38213a - boards/platforms/kc705: add user_sma_mgt_refclk <Florent Kermarrec>
    * |   4cdd6799 - Merge pull request #123 from cr1901/prv32-min <enjoy-digital>
    |\ \
    | * | e56f7182 - libbase/crt0-picorv32: Emulate support for a relocatable IRQ vector (hardcoded at synthesis time). <William D. Jones>
    | * | f32121e0 - cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector. <William D. Jones>
    | * | 77389d27 - libbase/crt0-picorv32: Ensure BSS is cleared on boot. <William D. Jones>
    | * | f69bd877 - cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations). <William D. Jones>
    | * | d05fe673 - cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs. <William D. Jones>
    * | | f7969b66 - cores/clock: add with_reset parameter (default to True) <Florent Kermarrec>
    | |/
    |/|
    * | 445c4940 - boards/platforms/kcu105: add sfp_tx/rx definition <Florent Kermarrec>
    |/
    * e9d4c882 - build/lattice/prjtrellis: fix default toolchain_path <Florent Kermarrec>
    * 468780c0 - soc/cores/spi_flash: add endianness parameter <Florent Kermarrec>
    * 6f3131e2 - soc/interconnect/stream_packet: use reverse_bytes from litex.gen <Florent Kermarrec>
    * b7968538 - gen: add common with reverse_bits/reverse_bytes functions <Florent Kermarrec>
    * 71fc34d7 - boards/targets/ulx3s: reduce l2_size <Florent Kermarrec>
    * 75d073f3 - build/lattice/prjtrellis: fix typo <Florent Kermarrec>
    * 6048a529 - build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper, handle inouts. <Florent Kermarrec>
    * 2243f628 - build/lattice/common: fix LatticeECPXPrjTrellisTristateImpl <Florent Kermarrec>
    *   3a8bb94a - Merge pull request #121 from cr1901/patch-3 <Tim Ansell>
    |\
    | * f3111e11 - Update vivado.py <William D. Jones>
    |/
    * 98fa8996 - boards/targets: add ulx3s <Florent Kermarrec>
    * 7d779473 - boards/platforms: add ulx3s <Florent Kermarrec>
    * d9dcad33 - build/lattice/prjtrellis: add inout support <Florent Kermarrec>
    * 091ad799 - build/lattice/common: add tristate support <Florent Kermarrec>
    * 23acefb1 - boards/targets/versaecp55g_prjtrellis: simple.py example working, specific target no longer needed <Florent Kermarrec>
    * 1097f822 - build/lattice/prjtrellis: set default toolchain_path to "/opt/prjtrellis" <Florent Kermarrec>
    * 52917a71 - boards/targets/simple: add gateware-toolchain parameter <Florent Kermarrec>
    * d84083f6 - boards/platforms/versaecp55g: use ftdi serial pins <Florent Kermarrec>
    * c05b9ef2 - build/lattice/prjtrellis: test and fix iowrapper multi-bit signals support <Florent Kermarrec>
    * a8f819fe - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    * 4eb314a2 - boards/targets/versaecp55g: use new iowrapper support, basic led blink and ios working :) <Florent Kermarrec>
    * 27ec2a59 - build/lattice/prjtrellis: generate iowrapper to set constraints and TRELLIS_IO <Florent Kermarrec>
    * c506c975 - gen/fhdl/verilog: set direction to io signals <Florent Kermarrec>

 * migen changed from 0.6.dev-179-g657c0c7 to 0.6.dev-187-gc79d988
    * c79d988 - build/platforms/versaecp55g: add X3 external connector. <whitequark>
    * d60cea0 - build/platforms/versaecp55g: add external clock input. <whitequark>
    * c51a064 - build/platforms/versaecp55g: allow programming without ispCLOCK in chain. <whitequark>
    * 34eeb3b - build/platforms/versaecp55g: import from litex. <whitequark>
    * 7bdc4ed - build/lattice/diamond: add Linux support. <whitequark>
    * 3a84a8b - build/lattice/diamond: only run Jedecgen for MachXO. <whitequark>
    * 966781b - class Tristate: add support for target parameter with oe, o and i subsignals. (#148) <Staf Verhaegen>
    * 907afd5 - platforms/icebreaker: Rename I/O w/ @esden's feedback. <William D. Jones>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 69ea8668d06f3973e2342a1f8bc3ace2ca37f808 litedram (remotes/origin/HEAD)
 52c23015b052e40600a84ac73227fb5a0f0ce862 liteeth (remotes/origin/HEAD)
 80f28b1dd4d67c37a3829fbeef725a3ca8efad79 litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 fc0d5c3963146f67ad03ba0c6bdf06a6b4a0cde6 litex (heads/master)
 c79d98882088ceb23b9095002d08ad93a81d0021 migen (0.6.dev-187-gc79d988)