Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/misoc
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 2520ab480b0b
Choose a base ref
...
head repository: m-labs/misoc
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 421fe08770b6
Choose a head ref
  • 3 commits
  • 2 files changed
  • 1 contributor

Commits on Nov 3, 2015

  1. Copy the full SHA
    d554a06 View commit details
  2. Copy the full SHA
    b340d7e View commit details
  3. Copy the full SHA
    421fe08 View commit details
Showing with 17 additions and 7 deletions.
  1. +1 −1 misoc/interconnect/wishbone.py
  2. +16 −6 misoc/targets/kc705.py
2 changes: 1 addition & 1 deletion misoc/interconnect/wishbone.py
Original file line number Diff line number Diff line change
@@ -641,7 +641,7 @@ def __init__(self, description, bus=None):

###

GenericBank.__init__(self, description, len(self.bus.dat_w))
csr.GenericBank.__init__(self, description, len(self.bus.dat_w))

for i, c in enumerate(self.simple_csrs):
self.comb += [
22 changes: 16 additions & 6 deletions misoc/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -83,7 +83,7 @@ class BaseSoC(SoCSDRAM):
}
csr_map.update(SoCSDRAM.csr_map)

def __init__(self, toolchain="ise", **kwargs):
def __init__(self, toolchain="ise", sdram_controller_type="minicon", **kwargs):
platform = kc705.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self, platform,
clk_freq=125*1000000, cpu_reset_address=0xaf0000,
@@ -94,7 +94,7 @@ def __init__(self, toolchain="ise", **kwargs):
if not self.integrated_main_ram_size:
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT8JTF12864(self.clk_freq)
self.register_sdram(self.ddrphy, "lasmicon",
self.register_sdram(self.ddrphy, sdram_controller_type,
sdram_module.geom_settings, sdram_module.timing_settings)

if not self.integrated_rom_size:
@@ -137,18 +137,28 @@ def __init__(self, *args, **kwargs):
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)


def main():
parser = argparse.ArgumentParser(description="MiSoC port to the KC705")
builder_args(parser)
def soc_kc705_args(parser):
soc_sdram_args(parser)
parser.add_argument("--toolchain", default="ise",
help="FPGA toolchain to use: ise, vivado")


def soc_kc705_argdict(args):
r = soc_sdram_argdict(args)
r["toolchain"] = args.toolchain
return r


def main():
parser = argparse.ArgumentParser(description="MiSoC port to the KC705")
builder_args(parser)
soc_kc705_args(parser)
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
args = parser.parse_args()

cls = MiniSoC if args.with_ethernet else BaseSoC
soc = cls(toolchain=args.toolchain, **soc_sdram_argdict(args))
soc = cls(**soc_kc705_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()