m-labs · Nov 3, 2015 · Nov 3, 2015 · Nov 3, 2015
Showing with 17 additions and 7 deletions.

+1 −1 misoc/interconnect/wishbone.py

+16 −6 misoc/targets/kc705.py
diff --git a/misoc/interconnect/wishbone.py b/misoc/interconnect/wishbone.py
@@ -641,7 +641,7 @@ def __init__(self, description, bus=None):
 
         ###
 
-        GenericBank.__init__(self, description, len(self.bus.dat_w))
+        csr.GenericBank.__init__(self, description, len(self.bus.dat_w))
 
         for i, c in enumerate(self.simple_csrs):
             self.comb += [

diff --git a/misoc/targets/kc705.py b/misoc/targets/kc705.py
@@ -83,7 +83,7 @@ class BaseSoC(SoCSDRAM):
     }
     csr_map.update(SoCSDRAM.csr_map)
 
-    def __init__(self, toolchain="ise", **kwargs):
+    def __init__(self, toolchain="ise", sdram_controller_type="minicon", **kwargs):
         platform = kc705.Platform(toolchain=toolchain)
         SoCSDRAM.__init__(self, platform,
                           clk_freq=125*1000000, cpu_reset_address=0xaf0000,
@@ -94,7 +94,7 @@ def __init__(self, toolchain="ise", **kwargs):
         if not self.integrated_main_ram_size:
             self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
             sdram_module = MT8JTF12864(self.clk_freq)
-            self.register_sdram(self.ddrphy, "lasmicon",
+            self.register_sdram(self.ddrphy, sdram_controller_type,
                                 sdram_module.geom_settings, sdram_module.timing_settings)
 
         if not self.integrated_rom_size:
@@ -137,18 +137,28 @@ def __init__(self, *args, **kwargs):
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 
 
-def main():
-    parser = argparse.ArgumentParser(description="MiSoC port to the KC705")
-    builder_args(parser)
+def soc_kc705_args(parser):
     soc_sdram_args(parser)
     parser.add_argument("--toolchain", default="ise",
                         help="FPGA toolchain to use: ise, vivado")
+
+
+def soc_kc705_argdict(args):
+    r = soc_sdram_argdict(args)
+    r["toolchain"] = args.toolchain
+    return r
+
+
+def main():
+    parser = argparse.ArgumentParser(description="MiSoC port to the KC705")
+    builder_args(parser)
+    soc_kc705_args(parser)
     parser.add_argument("--with-ethernet", action="store_true",
                         help="enable Ethernet support")
     args = parser.parse_args()
 
     cls = MiniSoC if args.with_ethernet else BaseSoC
-    soc = cls(toolchain=args.toolchain, **soc_sdram_argdict(args))
+    soc = cls(**soc_kc705_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()