Skip to content

Commit

Permalink
cores/dvi_sampler: fix imports
Browse files Browse the repository at this point in the history
sbourdeauducq committed Nov 1, 2015
1 parent ca9631f commit 2a81866
Showing 12 changed files with 53 additions and 41 deletions.
2 changes: 1 addition & 1 deletion misoc/cores/dvi_sampler/__init__.py
Original file line number Diff line number Diff line change
@@ -1 +1 @@
from misoc.dvisampler.core import DVISampler
from misoc.cores.dvi_sampler.core import DVISampler
5 changes: 2 additions & 3 deletions misoc/cores/dvi_sampler/analysis.py
Original file line number Diff line number Diff line change
@@ -2,10 +2,9 @@
from migen.genlib.cdc import MultiReg, PulseSynchronizer
from migen.genlib.fifo import AsyncFIFO
from migen.genlib.record import Record
from migen.bank.description import *
from migen.flow.actor import *

from misoc.dvisampler.common import channel_layout
from misoc.interconnect.csr import *
from misoc.cores.dvi_sampler.common import channel_layout


class SyncPolarity(Module):
12 changes: 7 additions & 5 deletions misoc/cores/dvi_sampler/chansync.py
Original file line number Diff line number Diff line change
@@ -1,11 +1,13 @@
from functools import reduce
from operator import or_, and_

from migen import *
from migen.genlib.cdc import MultiReg
from migen.genlib.fifo import _inc
from migen.genlib.record import Record, layout_len
from migen.genlib.misc import optree
from migen.bank.description import *

from misoc.dvisampler.common import channel_layout
from misoc.interconnect.csr import *
from misoc.cores.dvi_sampler.common import channel_layout


class _SyncBuffer(Module):
@@ -73,8 +75,8 @@ def __init__(self, nchan=3, depth=8):

some_control = Signal()
self.comb += [
all_control.eq(optree("&", lst_control)),
some_control.eq(optree("|", lst_control))
all_control.eq(reduce(and_, lst_control)),
some_control.eq(reduce(or_, lst_control))
]
self.sync.pix += If(~self.valid_i,
self.chan_synced.eq(0)
10 changes: 6 additions & 4 deletions misoc/cores/dvi_sampler/charsync.py
Original file line number Diff line number Diff line change
@@ -1,9 +1,11 @@
from functools import reduce
from operator import or_

from migen import *
from migen.genlib.cdc import MultiReg
from migen.genlib.misc import optree
from migen.bank.description import *

from misoc.dvisampler.common import control_tokens
from misoc.interconnect.csr import *
from misoc.cores.dvi_sampler.common import control_tokens


class CharSync(Module, AutoCSR):
@@ -26,7 +28,7 @@ def __init__(self, required_controls=8):
control_position = Signal(max=10)
self.sync.pix += found_control.eq(0)
for i in range(10):
self.sync.pix += If(optree("|", [raw[i:i+10] == t for t in control_tokens]),
self.sync.pix += If(reduce(or_, [raw[i:i+10] == t for t in control_tokens]),
found_control.eq(1),
control_position.eq(i)
)
3 changes: 2 additions & 1 deletion misoc/cores/dvi_sampler/clocking.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
from migen import *
from migen.genlib.cdc import MultiReg
from migen.bank.description import *

from misoc.interconnect.csr import *


class Clocking(Module, AutoCSR):
20 changes: 10 additions & 10 deletions misoc/cores/dvi_sampler/core.py
Original file line number Diff line number Diff line change
@@ -1,15 +1,15 @@
from migen import *
from migen.bank.description import AutoCSR

from misoc.dvisampler.edid import EDID
from misoc.dvisampler.clocking import Clocking
from misoc.dvisampler.datacapture import DataCapture
from misoc.dvisampler.charsync import CharSync
from misoc.dvisampler.wer import WER
from misoc.dvisampler.decoding import Decoding
from misoc.dvisampler.chansync import ChanSync
from misoc.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
from misoc.dvisampler.dma import DMA
from misoc.interconnect.csr import AutoCSR
from misoc.cores.dvi_sampler.edid import EDID
from misoc.cores.dvi_sampler.clocking import Clocking
from misoc.cores.dvi_sampler.datacapture import DataCapture
from misoc.cores.dvi_sampler.charsync import CharSync
from misoc.cores.dvi_sampler.wer import WER
from misoc.cores.dvi_sampler.decoding import Decoding
from misoc.cores.dvi_sampler.chansync import ChanSync
from misoc.cores.dvi_sampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
from misoc.cores.dvi_sampler.dma import DMA


class DVISampler(Module, AutoCSR):
3 changes: 2 additions & 1 deletion misoc/cores/dvi_sampler/datacapture.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
from migen import *
from migen.genlib.cdc import MultiReg, PulseSynchronizer
from migen.bank.description import *

from misoc.interconnect.csr import *


class DataCapture(Module, AutoCSR):
11 changes: 6 additions & 5 deletions misoc/cores/dvi_sampler/debug.py
Original file line number Diff line number Diff line change
@@ -1,13 +1,14 @@
from migen import *
from migen.genlib.fifo import AsyncFIFO
from migen.genlib.record import layout_len
from migen.bank.description import AutoCSR
from migen.actorlib import structuring, spi

from misoc.mem.sdram.frontend import dma_lasmi
from misoc.dvisampler.edid import EDID
from misoc.dvisampler.clocking import Clocking
from misoc.dvisampler.datacapture import DataCapture
from misoc.cores.dvi_sampler.edid import EDID
from misoc.cores.dvi_sampler.clocking import Clocking
from misoc.cores.dvi_sampler.datacapture import DataCapture

# TODO
#from misoc.mem.sdram.frontend import dma_lasmi


class RawDVISampler(Module, AutoCSR):
2 changes: 1 addition & 1 deletion misoc/cores/dvi_sampler/decoding.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
from migen import *
from migen.genlib.record import Record

from misoc.dvisampler.common import control_tokens, channel_layout
from misoc.cores.dvi_sampler.common import control_tokens, channel_layout


class Decoding(Module):
10 changes: 6 additions & 4 deletions misoc/cores/dvi_sampler/dma.py
Original file line number Diff line number Diff line change
@@ -1,10 +1,12 @@
from migen import *
from migen.genlib.fsm import FSM, NextState
from migen.bank.description import *
from migen.bank.eventmanager import *
from migen.flow.actor import *

from misoc.mem.sdram.frontend import dma_lasmi
from misoc.interconnect.csr import *
from misoc.interconnect.csr_eventmanager import *

# TODO: rewrite dma_lasmi module
# TODO: use stream packets to resync DMA
#from misoc.mem.sdram.frontend import dma_lasmi


# Slot status: EMPTY=0 LOADED=1 PENDING=2
4 changes: 3 additions & 1 deletion misoc/cores/dvi_sampler/edid.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,9 @@
from migen.genlib.cdc import MultiReg
from migen.genlib.fsm import FSM, NextState
from migen.genlib.misc import chooser
from migen.bank.description import CSRStorage, CSRStatus, AutoCSR

from misoc.interconnect.csr import CSRStorage, CSRStatus, AutoCSR


_default_edid = [
0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x32, 0x12, 0x2A, 0x6A, 0xBF, 0x00,
12 changes: 7 additions & 5 deletions misoc/cores/dvi_sampler/wer.py
Original file line number Diff line number Diff line change
@@ -1,9 +1,11 @@
from functools import reduce
from operator import add, or_

from migen import *
from migen.bank.description import *
from migen.genlib.misc import optree
from migen.genlib.cdc import PulseSynchronizer

from misoc.dvisampler.common import control_tokens
from misoc.interconnect.csr import *
from misoc.cores.dvi_sampler.common import control_tokens


class WER(Module, AutoCSR):
@@ -23,10 +25,10 @@ def __init__(self, period_bits=24):
transitions = Signal(8)
self.comb += [transitions[i].eq(data_r[i] ^ data_r[i+1]) for i in range(8)]
transition_count = Signal(max=9)
self.sync.pix += transition_count.eq(optree("+", [transitions[i] for i in range(8)]))
self.sync.pix += transition_count.eq(reduce(add, [transitions[i] for i in range(8)]))

is_control = Signal()
self.sync.pix += is_control.eq(optree("|", [data_r == ct for ct in control_tokens]))
self.sync.pix += is_control.eq(reduce(or_, [data_r == ct for ct in control_tokens]))

# pipeline stage 3
is_error = Signal()

0 comments on commit 2a81866

Please sign in to comment.