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wishbone: add read/write simulation methods
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sbourdeauducq committed Nov 3, 2015
1 parent c9d203a commit 2520ab4
Showing 1 changed file with 24 additions and 0 deletions.
24 changes: 24 additions & 0 deletions misoc/interconnect/wishbone.py
Original file line number Diff line number Diff line change
@@ -33,6 +33,30 @@ def __init__(self, data_width=32):
data_width=data_width,
sel_width=data_width//8))

def _do_transaction(self):
yield self.cyc.eq(1)
yield self.stb.eq(1)
yield
while not (yield self.ack):
yield
yield self.cyc.eq(0)
yield self.stb.eq(0)

def write(self, adr, dat, sel=None):
if sel is None:
sel = 2**len(self.sel) - 1
yield self.adr.eq(adr)
yield self.dat_w.eq(dat)
yield self.sel.eq(sel)
yield self.we.eq(1)
yield from self._do_transaction()

def read(self, adr):
yield self.adr.eq(adr)
yield self.we.eq(0)
yield from self._do_transaction()
return (yield self.dat_r)


class InterconnectPointToPoint(Module):
def __init__(self, master, slave):

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