Merge 'new' branch

m-labs · Nov 4, 2015 · da171d8 · da171d8
2 parents 0607e92 + 71fd951
commit da171d8
Showing 241 changed files with 3,173 additions and 3,011 deletions.
diff --git a/.gitignore b/.gitignore
@@ -1,15 +1,3 @@
 __pycache__
-build/*
-*.o
-*.d
-*.a
-*.elf
-*.bin
-*.fbi
-tools/flterm
-tools/byteswap
-software/include/generated/*.h
-software/include/generated/*.ld
-software/include/generated/*.mak
 *.vcd
 outgoing
diff --git a/.gitmodules b/.gitmodules
@@ -1,12 +1,12 @@
-[submodule "extcores/lm32/submodule"]
-	path = extcores/lm32/submodule
+[submodule "misoc/cores/lm32/verilog/submodule"]
+	path = misoc/cores/lm32/verilog/submodule
 	url = https://github.com/m-labs/lm32.git
-[submodule "extcores/mor1kx/submodule"]
-	path = extcores/mor1kx/submodule
-	url = https://github.com/openrisc/mor1kx.git
-[submodule "software/compiler-rt"]
-	path = software/compiler-rt
+[submodule "misoc/cores/mor1kx/verilog"]
+    path = misoc/cores/mor1kx/verilog
+    url = https://github.com/openrisc/mor1kx.git
+[submodule "misoc/software/compiler_rt"]
+	path = misoc/software/compiler_rt
 	url = http://llvm.org/git/compiler-rt.git
-[submodule "software/unwinder"]
-	path = software/unwinder
+[submodule "misoc/software/unwinder"]
+	path = misoc/software/unwinder
 	url = https://github.com/whitequark/libunwind
diff --git a/.travis.yml b/.travis.yml
@@ -0,0 +1,36 @@
+language: python
+python:
+  - "3.5"
+
+env:
+  global:
+    - PATH=$HOME/miniconda/bin:$PATH
+
+before_install:
+  # Install Miniconda
+  - wget https://raw.githubusercontent.com/m-labs/artiq/master/.travis/get-anaconda.sh
+  - chmod +x get-anaconda.sh
+  - ./get-anaconda.sh
+  - source $HOME/miniconda/bin/activate py35
+  - conda install anaconda-client
+install:
+  # workaround for https://github.com/conda/conda-build/issues/466
+  - "mkdir -p /home/travis/miniconda/conda-bld/linux-64"
+  - "conda index /home/travis/miniconda/conda-bld/linux-64"
+  - "conda build --python 3.5 conda/misoc"
+  - "conda install $(conda build --output --python 3.5 conda/misoc)"
+script:
+  - true
+
+after_success:
+  - if [ "${TRAVIS_PULL_REQUEST}" = "false" ]; then anaconda login --hostname $(hostname) --username $binstar_login --password $binstar_password; fi
+  - if [ "${TRAVIS_PULL_REQUEST}" = "false" ]; then anaconda upload --user $binstar_login --channel dev --force $HOME/miniconda/conda-bld/noarch/misoc-*.tar.bz2; fi
+
+notifications:
+  email: false
+  irc:
+    channels:
+      - chat.freenode.net#m-labs
+    template:
+      - "%{repository}#%{build_number} (%{branch} - %{commit} : %{author}): %{message}"
+      - "Build details : %{build_url}"
diff --git a/CONTRIBUTING.md → CONTRIBUTING.rst b/CONTRIBUTING.md → CONTRIBUTING.rst
diff --git a/MANIFEST.in b/MANIFEST.in
@@ -0,0 +1,4 @@
+graft misoc/software
+graft misoc/cores/lm32/verilog
+graft misoc/cores/mor1kx/verilog
+include misoc/cores/mxcrg.v
diff --git a/README b/README
@@ -106,7 +106,7 @@ modules.
 
 9. Contribute a patch!
   Once you have experimented with stuff, please send your results back.
-  For more details on how to do so, you can see the CONTRIBUTING.md file.
+  For more details on how to do so, you can see the CONTRIBUTING.rst file.
 
 [> License
 ----------

diff --git a/build/.keep_me b/build/.keep_me
diff --git a/conda/misoc/bld.bat b/conda/misoc/bld.bat
@@ -0,0 +1 @@
+%PYTHON% setup.py install
diff --git a/conda/misoc/meta.yaml b/conda/misoc/meta.yaml
@@ -0,0 +1,26 @@
+package:
+  name: misoc
+  version: {{ environ.get("GIT_DESCRIBE_TAG", "") }}
+
+source:
+  git_url: https://github.com/m-labs/misoc
+  git_tag: new
+
+build:
+  noarch_python: true
+  number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
+  string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_DESCRIBE_HASH", "")[1:] }}
+  script: $PYTHON setup.py install
+
+requirements:
+  build:
+    - migen
+    - python
+  run:
+    - migen
+    - python
+
+about:
+  home: http://m-labs.hk/gateware.html
+  license: 3-clause BSD
+  summary: 'A high performance and small footprint SoC based on Migen'
diff --git a/crc.py b/crc.py
diff --git a/extcores/__init__.py b/extcores/__init__.py
diff --git a/extcores/mor1kx/submodule b/extcores/mor1kx/submodule
diff --git a/flash_extra.py b/flash_extra.py
diff --git a/make.py b/make.py
diff --git a/targets/__init__.py → misoc/__init__.py b/targets/__init__.py → misoc/__init__.py
diff --git a/misoclib/video/__init__.py → misoc/cores/__init__.py b/misoclib/video/__init__.py → misoc/cores/__init__.py
diff --git a/misoclib/mem/sdram/phy/dfii.py → misoc/cores/dfii.py b/misoclib/mem/sdram/phy/dfii.py → misoc/cores/dfii.py
@@ -1,17 +1,17 @@
-from migen.fhdl.std import *
-from migen.bank.description import *
+from migen import *
 
-from misoclib.mem.sdram.phy import dfi
+from misoc.interconnect import dfi
+from misoc.interconnect.csr import *
 
 
 class PhaseInjector(Module, AutoCSR):
     def __init__(self, phase):
         self._command = CSRStorage(6)  # cs, we, cas, ras, wren, rden
         self._command_issue = CSR()
-        self._address = CSRStorage(flen(phase.address))
-        self._baddress = CSRStorage(flen(phase.bank))
-        self._wrdata = CSRStorage(flen(phase.wrdata))
-        self._rddata = CSRStatus(flen(phase.rddata))
+        self._address = CSRStorage(len(phase.address))
+        self._baddress = CSRStorage(len(phase.bank))
+        self._wrdata = CSRStorage(len(phase.wrdata))
+        self._rddata = CSRStatus(len(phase.rddata))
 
         ###
 

diff --git a/misoc/cores/dvi_sampler/__init__.py b/misoc/cores/dvi_sampler/__init__.py
@@ -0,0 +1 @@
+from misoc.cores.dvi_sampler.core import DVISampler
diff --git a/misoclib/video/dvisampler/analysis.py → misoc/cores/dvi_sampler/analysis.py b/misoclib/video/dvisampler/analysis.py → misoc/cores/dvi_sampler/analysis.py
@@ -1,11 +1,10 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.record import Record
-from migen.bank.description import *
-from migen.flow.actor import *
 
-from misoclib.video.dvisampler.common import channel_layout
+from misoc.interconnect.csr import *
+from misoc.cores.dvi_sampler.common import channel_layout
 
 
 class SyncPolarity(Module):

diff --git a/misoclib/video/dvisampler/chansync.py → misoc/cores/dvi_sampler/chansync.py b/misoclib/video/dvisampler/chansync.py → misoc/cores/dvi_sampler/chansync.py
@@ -1,11 +1,13 @@
-from migen.fhdl.std import *
+from functools import reduce
+from operator import or_, and_
+
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fifo import _inc
 from migen.genlib.record import Record, layout_len
-from migen.genlib.misc import optree
-from migen.bank.description import *
 
-from misoclib.video.dvisampler.common import channel_layout
+from misoc.interconnect.csr import *
+from misoc.cores.dvi_sampler.common import channel_layout
 
 
 class _SyncBuffer(Module):
@@ -73,8 +75,8 @@ def __init__(self, nchan=3, depth=8):
 
         some_control = Signal()
         self.comb += [
-            all_control.eq(optree("&", lst_control)),
-            some_control.eq(optree("|", lst_control))
+            all_control.eq(reduce(and_, lst_control)),
+            some_control.eq(reduce(or_, lst_control))
         ]
         self.sync.pix += If(~self.valid_i,
                 self.chan_synced.eq(0)

diff --git a/misoclib/video/dvisampler/charsync.py → misoc/cores/dvi_sampler/charsync.py b/misoclib/video/dvisampler/charsync.py → misoc/cores/dvi_sampler/charsync.py
@@ -1,9 +1,11 @@
-from migen.fhdl.std import *
+from functools import reduce
+from operator import or_
+
+from migen import *
 from migen.genlib.cdc import MultiReg
-from migen.genlib.misc import optree
-from migen.bank.description import *
 
-from misoclib.video.dvisampler.common import control_tokens
+from misoc.interconnect.csr import *
+from misoc.cores.dvi_sampler.common import control_tokens
 
 
 class CharSync(Module, AutoCSR):
@@ -26,7 +28,7 @@ def __init__(self, required_controls=8):
         control_position = Signal(max=10)
         self.sync.pix += found_control.eq(0)
         for i in range(10):
-            self.sync.pix += If(optree("|", [raw[i:i+10] == t for t in control_tokens]),
+            self.sync.pix += If(reduce(or_, [raw[i:i+10] == t for t in control_tokens]),
                   found_control.eq(1),
                   control_position.eq(i)
             )

diff --git a/misoclib/video/dvisampler/clocking.py → misoc/cores/dvi_sampler/clocking.py b/misoclib/video/dvisampler/clocking.py → misoc/cores/dvi_sampler/clocking.py
@@ -1,6 +1,7 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
-from migen.bank.description import *
+
+from misoc.interconnect.csr import *
 
 
 class Clocking(Module, AutoCSR):

diff --git a/misoclib/video/dvisampler/common.py → misoc/cores/dvi_sampler/common.py b/misoclib/video/dvisampler/common.py → misoc/cores/dvi_sampler/common.py
diff --git a/misoclib/video/dvisampler/__init__.py → misoc/cores/dvi_sampler/core.py b/misoclib/video/dvisampler/__init__.py → misoc/cores/dvi_sampler/core.py
@@ -1,15 +1,15 @@
-from migen.fhdl.std import *
-from migen.bank.description import AutoCSR
+from migen import *
 
-from misoclib.video.dvisampler.edid import EDID
-from misoclib.video.dvisampler.clocking import Clocking
-from misoclib.video.dvisampler.datacapture import DataCapture
-from misoclib.video.dvisampler.charsync import CharSync
-from misoclib.video.dvisampler.wer import WER
-from misoclib.video.dvisampler.decoding import Decoding
-from misoclib.video.dvisampler.chansync import ChanSync
-from misoclib.video.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
-from misoclib.video.dvisampler.dma import DMA
+from misoc.interconnect.csr import AutoCSR
+from misoc.cores.dvi_sampler.edid import EDID
+from misoc.cores.dvi_sampler.clocking import Clocking
+from misoc.cores.dvi_sampler.datacapture import DataCapture
+from misoc.cores.dvi_sampler.charsync import CharSync
+from misoc.cores.dvi_sampler.wer import WER
+from misoc.cores.dvi_sampler.decoding import Decoding
+from misoc.cores.dvi_sampler.chansync import ChanSync
+from misoc.cores.dvi_sampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
+from misoc.cores.dvi_sampler.dma import DMA
 
 
 class DVISampler(Module, AutoCSR):

diff --git a/misoclib/video/dvisampler/datacapture.py → misoc/cores/dvi_sampler/datacapture.py b/misoclib/video/dvisampler/datacapture.py → misoc/cores/dvi_sampler/datacapture.py
@@ -1,6 +1,7 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
-from migen.bank.description import *
+
+from misoc.interconnect.csr import *
 
 
 class DataCapture(Module, AutoCSR):

diff --git a/misoclib/video/dvisampler/debug.py → misoc/cores/dvi_sampler/debug.py b/misoclib/video/dvisampler/debug.py → misoc/cores/dvi_sampler/debug.py
@@ -1,13 +1,14 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fifo import AsyncFIFO
-from migen.genlib.record import layout_len
 from migen.bank.description import AutoCSR
 from migen.actorlib import structuring, spi
 
-from misoclib.mem.sdram.frontend import dma_lasmi
-from misoclib.video.dvisampler.edid import EDID
-from misoclib.video.dvisampler.clocking import Clocking
-from misoclib.video.dvisampler.datacapture import DataCapture
+from misoc.cores.dvi_sampler.edid import EDID
+from misoc.cores.dvi_sampler.clocking import Clocking
+from misoc.cores.dvi_sampler.datacapture import DataCapture
+
+# TODO
+#from misoc.mem.sdram.frontend import dma_lasmi
 
 
 class RawDVISampler(Module, AutoCSR):

diff --git a/misoclib/video/dvisampler/decoding.py → misoc/cores/dvi_sampler/decoding.py b/misoclib/video/dvisampler/decoding.py → misoc/cores/dvi_sampler/decoding.py
@@ -1,7 +1,7 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import Record
 
-from misoclib.video.dvisampler.common import control_tokens, channel_layout
+from misoc.cores.dvi_sampler.common import control_tokens, channel_layout
 
 
 class Decoding(Module):

diff --git a/misoclib/video/dvisampler/dma.py → misoc/cores/dvi_sampler/dma.py b/misoclib/video/dvisampler/dma.py → misoc/cores/dvi_sampler/dma.py
@@ -1,10 +1,12 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fsm import FSM, NextState
-from migen.bank.description import *
-from migen.bank.eventmanager import *
-from migen.flow.actor import *
 
-from misoclib.mem.sdram.frontend import dma_lasmi
+from misoc.interconnect.csr import *
+from misoc.interconnect.csr_eventmanager import *
+
+# TODO: rewrite dma_lasmi module
+# TODO: use stream packets to resync DMA
+#from misoc.mem.sdram.frontend import dma_lasmi
 
 
 # Slot status: EMPTY=0 LOADED=1 PENDING=2

diff --git a/misoclib/video/dvisampler/edid.py → misoc/cores/dvi_sampler/edid.py b/misoclib/video/dvisampler/edid.py → misoc/cores/dvi_sampler/edid.py
@@ -1,9 +1,11 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl.specials import Tristate
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.misc import chooser
-from migen.bank.description import CSRStorage, CSRStatus, AutoCSR
+
+from misoc.interconnect.csr import CSRStorage, CSRStatus, AutoCSR
+
 
 _default_edid = [
     0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x32, 0x12, 0x2A, 0x6A, 0xBF, 0x00,

diff --git a/misoclib/video/dvisampler/wer.py → misoc/cores/dvi_sampler/wer.py b/misoclib/video/dvisampler/wer.py → misoc/cores/dvi_sampler/wer.py
@@ -1,9 +1,11 @@
-from migen.fhdl.std import *
-from migen.bank.description import *
-from migen.genlib.misc import optree
+from functools import reduce
+from operator import add, or_
+
+from migen import *
 from migen.genlib.cdc import PulseSynchronizer
 
-from misoclib.video.dvisampler.common import control_tokens
+from misoc.interconnect.csr import *
+from misoc.cores.dvi_sampler.common import control_tokens
 
 
 class WER(Module, AutoCSR):
@@ -23,10 +25,10 @@ def __init__(self, period_bits=24):
         transitions = Signal(8)
         self.comb += [transitions[i].eq(data_r[i] ^ data_r[i+1]) for i in range(8)]
         transition_count = Signal(max=9)
-        self.sync.pix += transition_count.eq(optree("+", [transitions[i] for i in range(8)]))
+        self.sync.pix += transition_count.eq(reduce(add, [transitions[i] for i in range(8)]))
 
         is_control = Signal()
-        self.sync.pix += is_control.eq(optree("|", [data_r == ct for ct in control_tokens]))
+        self.sync.pix += is_control.eq(reduce(or_, [data_r == ct for ct in control_tokens]))
 
         # pipeline stage 3
         is_error = Signal()

diff --git a/misoc/cores/framebuffer/__init__.py b/misoc/cores/framebuffer/__init__.py
@@ -0,0 +1 @@
+from misoc.cores.framebuffer.core import Framebuffer
diff --git a/misoclib/video/framebuffer/__init__.py → misoc/cores/framebuffer/core.py b/misoclib/video/framebuffer/__init__.py → misoc/cores/framebuffer/core.py
@@ -1,12 +1,12 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.flow.network import *
 from migen.flow import plumbing
 from migen.bank.description import AutoCSR
 from migen.actorlib import structuring, misc
 
-from misoclib.mem.sdram.frontend import dma_lasmi
-from misoclib.video.framebuffer.format import bpp, pixel_layout, FrameInitiator, VTG
-from misoclib.video.framebuffer.phy import Driver
+from misoc.mem.sdram.frontend import dma_lasmi
+from misoc.framebuffer.format import bpp, pixel_layout, FrameInitiator, VTG
+from misoc.framebuffer.phy import Driver
 
 
 class Framebuffer(Module, AutoCSR):

diff --git a/misoclib/video/framebuffer/dvi.py → misoc/cores/framebuffer/dvi.py b/misoclib/video/framebuffer/dvi.py → misoc/cores/framebuffer/dvi.py
@@ -1,5 +1,8 @@
-from migen.fhdl.std import *
-from migen.genlib.misc import optree
+from functools import reduce
+from operator import add
+
+from migen import *
+
 
 control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]
 
@@ -18,7 +21,7 @@ def __init__(self):
         d = Signal(8)
         n1d = Signal(max=9)
         self.sync += [
-            n1d.eq(optree("+", [self.d[i] for i in range(8)])),
+            n1d.eq(reduce(add, [self.d[i] for i in range(8)])),
             d.eq(self.d)
         ]
 
@@ -39,8 +42,8 @@ def __init__(self):
         n0q_m = Signal(max=9)
         n1q_m = Signal(max=9)
         self.sync += [
-            n0q_m.eq(optree("+", [~q_m[i] for i in range(8)])),
-            n1q_m.eq(optree("+", [q_m[i] for i in range(8)])),
+            n0q_m.eq(reduce(add, [~q_m[i] for i in range(8)])),
+            n1q_m.eq(reduce(add, [q_m[i] for i in range(8)])),
             q_m_r.eq(q_m)
         ]
 

diff --git a/misoclib/video/framebuffer/format.py → misoc/cores/framebuffer/format.py b/misoclib/video/framebuffer/format.py → misoc/cores/framebuffer/format.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.flow.actor import *
 from migen.bank.description import CSRStorage
 from migen.genlib.record import Record

diff --git a/misoclib/video/framebuffer/phy.py → misoc/cores/framebuffer/phy.py b/misoclib/video/framebuffer/phy.py → misoc/cores/framebuffer/phy.py
@@ -1,11 +1,11 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 from migen.flow.actor import *
 
-from misoclib.video.framebuffer.format import bpc_phy, phy_layout
-from misoclib.video.framebuffer import dvi
+from misoc.framebuffer.format import bpc_phy, phy_layout
+from misoc.framebuffer import dvi
 
 
 class _FIFO(Module):

diff --git a/misoclib/com/gpio.py → misoc/cores/gpio.py b/misoclib/com/gpio.py → misoc/cores/gpio.py
@@ -1,17 +1,18 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
-from migen.bank.description import *
+
+from misoc.interconnect.csr import *
 
 
 class GPIOIn(Module, AutoCSR):
     def __init__(self, signal):
-        self._in = CSRStatus(flen(signal))
+        self._in = CSRStatus(len(signal))
         self.specials += MultiReg(signal, self._in.status)
 
 
 class GPIOOut(Module, AutoCSR):
     def __init__(self, signal):
-        self._out = CSRStorage(flen(signal))
+        self._out = CSRStorage(len(signal))
         self.comb += signal.eq(self._out.storage)
 
 

diff --git a/misoc/cores/identifier.py b/misoc/cores/identifier.py
@@ -0,0 +1,16 @@
+from migen import *
+
+from misoc.interconnect.csr import *
+
+
+class Identifier(Module, AutoCSR):
+    def __init__(self, sysid, frequency, revision=None):
+        self._sysid = CSRStatus(16)
+        self._frequency = CSRStatus(32)
+
+        ###
+
+        self.comb += [
+            self._sysid.status.eq(sysid),
+            self._frequency.status.eq(frequency)
+        ]
diff --git a/misoc/cores/lasmicon/__init__.py b/misoc/cores/lasmicon/__init__.py
@@ -0,0 +1 @@
+from misoc.cores.lasmicon.core import ControllerSettings, LASMIcon
diff --git a/...ib/mem/sdram/core/lasmicon/bankmachine.py → misoc/cores/lasmicon/bankmachine.py b/...ib/mem/sdram/core/lasmicon/bankmachine.py → misoc/cores/lasmicon/bankmachine.py
@@ -1,10 +1,9 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.roundrobin import *
 from migen.genlib.fsm import FSM, NextState
-from migen.genlib.misc import optree
 from migen.genlib.fifo import SyncFIFO
 
-from misoclib.mem.sdram.core.lasmicon.multiplexer import *
+from misoc.cores.lasmicon.multiplexer import *
 
 
 class _AddressSlicer:
@@ -36,18 +35,24 @@ def __init__(self, geom_settings, timing_settings, controller_settings, address_
         ###
 
         # Request FIFO
-        self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", flen(req.adr))],
+        layout = [("we", 1), ("adr", len(req.adr))]
+        req_in = Record(layout)
+        reqf = Record(layout)
+        self.submodules.req_fifo = SyncFIFO(layout_len(layout),
                                             controller_settings.req_queue_size)
         self.comb += [
-            self.req_fifo.din.we.eq(req.we),
-            self.req_fifo.din.adr.eq(req.adr),
+            self.req_fifo.din.eq(req_in.raw_bits()),
+            reqf.raw_bits().eq(self.req_fifo.dout)
+        ]
+        self.comb += [
+            req_in.we.eq(req.we),
+            req_in.adr.eq(req.adr),
             self.req_fifo.we.eq(req.stb),
             req.req_ack.eq(self.req_fifo.writable),
 
             self.req_fifo.re.eq(req.dat_w_ack | req.dat_r_ack),
             req.lock.eq(self.req_fifo.readable)
         ]
-        reqf = self.req_fifo.dout
 
         slicer = _AddressSlicer(geom_settings.colbits, address_align)
 

diff --git a/misoclib/mem/sdram/core/lasmicon/__init__.py → misoc/cores/lasmicon/core.py b/misoclib/mem/sdram/core/lasmicon/__init__.py → misoc/cores/lasmicon/core.py
@@ -1,33 +1,24 @@
-from migen.fhdl.std import *
-
-from misoclib.mem.sdram.phy import dfi
-from misoclib.mem.sdram.core import lasmibus
-from misoclib.mem.sdram.core.lasmicon.refresher import *
-from misoclib.mem.sdram.core.lasmicon.bankmachine import *
-from misoclib.mem.sdram.core.lasmicon.multiplexer import *
-
-
-class LASMIconSettings:
-    def __init__(self, req_queue_size=8,
-            read_time=32, write_time=16,
-            l2_size=8192,
-            with_bandwidth=False,
-            with_memtest=False,
-            with_refresh=True):
+from migen import *
+
+from misoc.interconnect import dfi, lasmi_bus
+from misoc.cores.lasmicon.refresher import *
+from misoc.cores.lasmicon.bankmachine import *
+from misoc.cores.lasmicon.multiplexer import *
+
+
+class ControllerSettings:
+    def __init__(self, req_queue_size=8, read_time=32, write_time=16, with_bandwidth=False):
         self.req_queue_size = req_queue_size
         self.read_time = read_time
         self.write_time = write_time
-        self.l2_size = l2_size
-        if with_memtest:
-            self.with_bandwidth = True
-        else:
-            self.with_bandwidth = with_bandwidth
-        self.with_memtest = with_memtest
-        self.with_refresh = with_refresh
+        self.with_bandwidth = with_bandwidth
 
 
 class LASMIcon(Module):
-    def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, **kwargs):
+    def __init__(self, phy_settings, geom_settings, timing_settings,
+                 controller_settings=None):
+        if controller_settings is None:
+            controller_settings = ControllerSettings()
         if phy_settings.memtype in ["SDR"]:
             burst_length = phy_settings.nphases*1  # command multiplication*SDR
         elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
@@ -38,7 +29,7 @@ def __init__(self, phy_settings, geom_settings, timing_settings, controller_sett
             geom_settings.bankbits,
             phy_settings.dfi_databits,
             phy_settings.nphases)
-        self.lasmic = lasmibus.Interface(
+        self.lasmic = lasmi_bus.Interface(
             aw=geom_settings.rowbits + geom_settings.colbits - address_align,
             dw=phy_settings.dfi_databits*phy_settings.nphases,
             nbanks=2**geom_settings.bankbits,
@@ -50,14 +41,13 @@ def __init__(self, phy_settings, geom_settings, timing_settings, controller_sett
         ###
 
         self.submodules.refresher = Refresher(geom_settings.addressbits, geom_settings.bankbits,
-            timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC, enabled=controller_settings.with_refresh)
+            timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC)
         self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, controller_settings, address_align, i,
                 getattr(self.lasmic, "bank"+str(i)))
             for i in range(2**geom_settings.bankbits)]
         self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings, controller_settings,
             self.bank_machines, self.refresher,
-            self.dfi, self.lasmic,
-            **kwargs)
+            self.dfi, self.lasmic)
 
     def get_csrs(self):
         return self.multiplexer.get_csrs()
diff --git a/...ib/mem/sdram/core/lasmicon/multiplexer.py → misoc/cores/lasmicon/multiplexer.py b/...ib/mem/sdram/core/lasmicon/multiplexer.py → misoc/cores/lasmicon/multiplexer.py
@@ -1,10 +1,12 @@
-from migen.fhdl.std import *
+from functools import reduce
+from operator import or_, and_
+
+from migen import *
 from migen.genlib.roundrobin import *
-from migen.genlib.misc import optree
 from migen.genlib.fsm import FSM, NextState
-from migen.bank.description import AutoCSR
 
-from misoclib.mem.sdram.core.lasmicon.perf import Bandwidth
+from misoc.cores.lasmicon.perf import Bandwidth
+from misoc.interconnect.csr import AutoCSR
 
 
 class CommandRequest:
@@ -32,7 +34,7 @@ def __init__(self, requests):
         self.want_writes = Signal()
         self.want_cmds = Signal()
         # NB: cas_n/ras_n/we_n are 1 when stb is inactive
-        self.cmd = CommandRequestRW(flen(requests[0].a), flen(requests[0].ba))
+        self.cmd = CommandRequestRW(len(requests[0].a), len(requests[0].ba))
 
         ###
 
@@ -124,8 +126,8 @@ def __init__(self, phy_settings, geom_settings, timing_settings, controller_sett
         read_available = Signal()
         write_available = Signal()
         self.comb += [
-            read_available.eq(optree("|", [req.stb & req.is_read for req in requests])),
-            write_available.eq(optree("|", [req.stb & req.is_write for req in requests]))
+            read_available.eq(reduce(or_, [req.stb & req.is_read for req in requests])),
+            write_available.eq(reduce(or_, [req.stb & req.is_write for req in requests]))
         ]
 
         def anti_starvation(timeout):
@@ -149,7 +151,7 @@ def anti_starvation(timeout):
         # Refresh
         self.comb += [bm.refresh_req.eq(refresher.req) for bm in bank_machines]
         go_to_refresh = Signal()
-        self.comb += go_to_refresh.eq(optree("&", [bm.refresh_gnt for bm in bank_machines]))
+        self.comb += go_to_refresh.eq(reduce(and_, [bm.refresh_gnt for bm in bank_machines]))
 
         # Datapath
         all_rddata = [p.rddata for p in dfi.phases]
@@ -209,20 +211,12 @@ def steerer_sel(steerer, phy_settings, r_w_n):
         )
         fsm.act("REFRESH",
             steerer.sel[0].eq(STEER_REFRESH),
+            refresher.ack.eq(1),
             If(~refresher.req, NextState("READ"))
         )
         fsm.delayed_enter("RTW", "WRITE", phy_settings.read_latency-1)  # FIXME: reduce this, actual limit is around (cl+1)/nphases
         fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1)
-        # FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
-        fsm.finalize()
-        self.comb += refresher.ack.eq(fsm.state == fsm.encoding["REFRESH"])
-
-        self.with_bandwidth = with_bandwidth
-
-    def add_bandwidth(self):
-        self.with_bandwidth = True
 
-    def do_finalize(self):
-        if self.with_bandwidth:
-            data_width = self.phy_settings.dfi_databits*self.phy_settings.nphases
+        if controller_settings.with_bandwidth:
+            data_width = phy_settings.dfi_databits*phy_settings.nphases
             self.submodules.bandwidth = Bandwidth(self.choose_req.cmd, data_width)
diff --git a/misoclib/mem/sdram/core/lasmicon/perf.py → misoc/cores/lasmicon/perf.py b/misoclib/mem/sdram/core/lasmicon/perf.py → misoc/cores/lasmicon/perf.py
@@ -1,5 +1,6 @@
-from migen.fhdl.std import *
-from migen.bank.description import *
+from migen import *
+
+from misoc.interconnect.csr import *
 
 
 class Bandwidth(Module, AutoCSR):

diff --git a/misoc/cores/lasmicon/refresher.py b/misoc/cores/lasmicon/refresher.py
@@ -0,0 +1,69 @@
+from migen import *
+from migen.genlib.misc import timeline
+from migen.genlib.fsm import FSM
+
+from misoc.cores.lasmicon.multiplexer import *
+
+
+class Refresher(Module):
+    def __init__(self, a, ba, tRP, tREFI, tRFC):
+        self.req = Signal()
+        self.ack = Signal()  # 1st command 1 cycle after assertion of ack
+        self.cmd = CommandRequest(a, ba)
+
+        ###
+
+        # Refresh sequence generator:
+        # PRECHARGE ALL --(tRP)--> AUTO REFRESH --(tRFC)--> done
+        seq_start = Signal()
+        seq_done = Signal()
+        self.sync += [
+            self.cmd.a.eq(2**10),
+            self.cmd.ba.eq(0),
+            self.cmd.cas_n.eq(1),
+            self.cmd.ras_n.eq(1),
+            self.cmd.we_n.eq(1),
+            seq_done.eq(0)
+        ]
+        self.sync += timeline(seq_start, [
+            (1, [
+                self.cmd.ras_n.eq(0),
+                self.cmd.we_n.eq(0)
+            ]),
+            (1+tRP, [
+                self.cmd.cas_n.eq(0),
+                self.cmd.ras_n.eq(0)
+            ]),
+            (1+tRP+tRFC, [
+                seq_done.eq(1)
+            ])
+        ])
+
+        # Periodic refresh counter
+        counter = Signal(max=tREFI)
+        start = Signal()
+        self.sync += [
+            start.eq(0),
+            If(counter == 0,
+                start.eq(1),
+                counter.eq(tREFI - 1)
+            ).Else(
+                counter.eq(counter - 1)
+            )
+        ]
+
+        # Control FSM
+        fsm = FSM()
+        self.submodules += fsm
+        fsm.act("IDLE", If(start, NextState("WAIT_GRANT")))
+        fsm.act("WAIT_GRANT",
+            self.req.eq(1),
+            If(self.ack,
+                seq_start.eq(1),
+                NextState("WAIT_SEQ")
+            )
+        )
+        fsm.act("WAIT_SEQ",
+            self.req.eq(1),
+            If(seq_done, NextState("IDLE"))
+        )
diff --git a/misoclib/mem/sdram/test/bankmachine_tb.py → misoc/cores/lasmicon/test_bankmachine.py b/misoclib/mem/sdram/test/bankmachine_tb.py → misoc/cores/lasmicon/test_bankmachine.py
@@ -1,10 +1,10 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.code import lasmibus
-from misoclib.mem.sdram.core.lasmicon.bankmachine import *
+from misoc.mem.sdram.code import lasmibus
+from misoc.mem.sdram.core.lasmicon.bankmachine import *
 
-from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger
+from test_common import sdram_phy, sdram_geom, sdram_timing, CommandLogger
 
 
 def my_generator():

diff --git a/misoclib/mem/sdram/test/common.py → misoc/cores/lasmicon/test_common.py b/misoclib/mem/sdram/test/common.py → misoc/cores/lasmicon/test_common.py
@@ -1,9 +1,9 @@
 from fractions import Fraction
 from math import ceil
 
-from migen.fhdl.std import *
+from migen import *
 
-from misoclib import sdram
+from misoc import sdram
 
 MHz = 1000000
 clk_freq = (83 + Fraction(1, 3))*MHz

diff --git a/misoclib/mem/sdram/test/lasmicon_df_tb.py → misoc/cores/lasmicon/test_df.py b/misoclib/mem/sdram/test/lasmicon_df_tb.py → misoc/cores/lasmicon/test_df.py
@@ -1,11 +1,11 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.core import lasmibus
-from misoclib.mem.sdram.core.lasmicon import *
-from misoclib.mem.sdram.frontend import dma_lasmi
+from misoc.mem.sdram.core import lasmibus
+from misoc.mem.sdram.core.lasmicon import *
+from misoc.mem.sdram.frontend import dma_lasmi
 
-from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
+from test_common import sdram_phy, sdram_geom, sdram_timing, DFILogger
 
 
 class TB(Module):

diff --git a/misoclib/mem/sdram/test/lasmicon_tb.py → misoc/cores/lasmicon/test_lasmi.py b/misoclib/mem/sdram/test/lasmicon_tb.py → misoc/cores/lasmicon/test_lasmi.py
@@ -1,10 +1,10 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.core import lasmibus
-from misoclib.mem.sdram.core.lasmicon import *
+from misoc.mem.sdram.core import lasmibus
+from misoc.mem.sdram.core.lasmicon import *
 
-from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
+from test_common import sdram_phy, sdram_geom, sdram_timing, DFILogger
 
 
 def my_generator_r(n):

diff --git a/misoclib/mem/sdram/test/refresher.py → misoc/cores/lasmicon/test_refresher.py b/misoclib/mem/sdram/test/refresher.py → misoc/cores/lasmicon/test_refresher.py
@@ -1,9 +1,9 @@
 from random import Random
 
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.core.lasmicon.refresher import *
+from misoc.mem.sdram.core.lasmicon.refresher import *
 
 from common import CommandLogger
 

diff --git a/misoclib/mem/sdram/test/lasmicon_wb.py → misoc/cores/lasmicon/test_wb.py b/misoclib/mem/sdram/test/lasmicon_wb.py → misoc/cores/lasmicon/test_wb.py
@@ -1,13 +1,13 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.core import lasmibus
-from misoclib.mem.sdram.core.lasmicon import *
-from misoclib.mem.sdram.frontend import wishbone2lasmi
+from misoc.mem.sdram.core import lasmibus
+from misoc.mem.sdram.core.lasmicon import *
+from misoc.mem.sdram.frontend import wishbone2lasmi
 
-from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
+from test_common import sdram_phy, sdram_geom, sdram_timing, DFILogger
 
 l2_size = 8192  # in bytes
 

diff --git a/misoclib/com/liteethmini/LICENSE → misoc/cores/liteeth_mini/LICENSE b/misoclib/com/liteethmini/LICENSE → misoc/cores/liteeth_mini/LICENSE
diff --git a/misoclib/com/liteethmini/README → misoc/cores/liteeth_mini/README b/misoclib/com/liteethmini/README → misoc/cores/liteeth_mini/README
diff --git a/misoclib/tools/__init__.py → misoc/cores/liteeth_mini/__init__.py b/misoclib/tools/__init__.py → misoc/cores/liteeth_mini/__init__.py
diff --git a/misoclib/com/liteethmini/common.py → misoc/cores/liteeth_mini/common.py b/misoclib/com/liteethmini/common.py → misoc/cores/liteeth_mini/common.py
@@ -1,16 +1,9 @@
-import math
-from collections import OrderedDict
-
-from migen.fhdl.std import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen import *
 from migen.genlib.record import *
-from migen.genlib.fsm import FSM, NextState
-from migen.genlib.misc import chooser, reverse_bytes, FlipFlop, Counter, WaitTimer
-from migen.flow.actor import *
-from migen.actorlib.structuring import Converter, Pipeline
-from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
-from migen.actorlib.packet import *
-from migen.bank.description import *
+
+from misoc.interconnect.csr import *
+from misoc.interconnect.stream import *
+
 
 class Port:
     def connect(self, port):
@@ -26,6 +19,7 @@ def connect(self, port):
 eth_preamble = 0xD555555555555555
 buffer_depth = 2**log2_int(eth_mtu, need_pow2=False)
 
+
 def eth_phy_description(dw):
     payload_layout = [
         ("data", dw),

diff --git a/misoclib/com/liteethmini/mac/__init__.py → misoc/cores/liteeth_mini/mac/__init__.py b/misoclib/com/liteethmini/mac/__init__.py → misoc/cores/liteeth_mini/mac/__init__.py
@@ -1,6 +1,9 @@
-from misoclib.com.liteethmini.common import *
-from misoclib.com.liteethmini.mac.core import LiteEthMACCore
-from misoclib.com.liteethmini.mac.frontend.wishbone import LiteEthMACWishboneInterface
+from migen import *
+
+from misoc.interconnect.csr import *
+from misoc.cores.liteeth_mini.common import *
+from misoc.cores.liteeth_mini.mac.core import LiteEthMACCore
+from misoc.cores.liteeth_mini.mac.frontend.wishbone import LiteEthMACWishboneInterface
 
 
 class LiteEthMAC(Module, AutoCSR):

diff --git a/...clib/com/liteethmini/mac/core/__init__.py → ...c/cores/liteeth_mini/mac/core/__init__.py b/...clib/com/liteethmini/mac/core/__init__.py → ...c/cores/liteeth_mini/mac/core/__init__.py
@@ -1,7 +1,9 @@
-from misoclib.com.liteethmini.common import *
-from misoclib.com.liteethmini.mac.core import gap, preamble, crc, padding, last_be
-from misoclib.com.liteethmini.phy.sim import LiteEthPHYSim
-from misoclib.com.liteethmini.phy.mii import LiteEthPHYMII
+from migen import *
+
+from misoc.interconnect.csr import *
+from misoc.cores.liteeth_mini.common import *
+from misoc.cores.liteeth_mini.mac.core import gap, preamble, crc, padding, last_be
+from misoc.cores.liteeth_mini.phy.mii import LiteEthPHYMII
 
 
 class LiteEthMACCore(Module, AutoCSR):
@@ -17,30 +19,26 @@ def __init__(self, phy, dw, endianness="big",
         # Interpacket gap
         tx_gap_inserter = gap.LiteEthMACGap(phy.dw)
         rx_gap_checker = gap.LiteEthMACGap(phy.dw, ack_on_gap=True)
-        self.submodules += RenameClockDomains(tx_gap_inserter, "eth_tx")
-        self.submodules += RenameClockDomains(rx_gap_checker, "eth_rx")
+        self.submodules += ClockDomainsRenamer("eth_tx")(tx_gap_inserter)
+        self.submodules += ClockDomainsRenamer("eth_rx")(rx_gap_checker)
 
         tx_pipeline += [tx_gap_inserter]
         rx_pipeline += [rx_gap_checker]
 
         # Preamble / CRC
-        if isinstance(phy, LiteEthPHYSim):
-            # In simulation, avoid CRC/Preamble to enable direct connection
-            # to the Ethernet tap.
-            self._preamble_crc = CSRStatus(reset=1)
-        elif with_preamble_crc:
+        if with_preamble_crc:
             self._preamble_crc = CSRStatus(reset=1)
             # Preamble insert/check
             preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw)
             preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw)
-            self.submodules += RenameClockDomains(preamble_inserter, "eth_tx")
-            self.submodules += RenameClockDomains(preamble_checker, "eth_rx")
+            self.submodules += ClockDomainsRenamer("eth_tx")(preamble_inserter)
+            self.submodules += ClockDomainsRenamer("eth_rx")(preamble_checker)
 
             # CRC insert/check
             crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw))
             crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw))
-            self.submodules += RenameClockDomains(crc32_inserter, "eth_tx")
-            self.submodules += RenameClockDomains(crc32_checker, "eth_rx")
+            self.submodules += ClockDomainsRenamer("eth_tx")(crc32_inserter)
+            self.submodules += ClockDomainsRenamer("eth_rx")(crc32_checker)
 
             tx_pipeline += [preamble_inserter, crc32_inserter]
             rx_pipeline += [preamble_checker, crc32_checker]
@@ -49,8 +47,8 @@ def __init__(self, phy, dw, endianness="big",
         if with_padding:
             padding_inserter = padding.LiteEthMACPaddingInserter(phy.dw, 60)
             padding_checker = padding.LiteEthMACPaddingChecker(phy.dw, 60)
-            self.submodules += RenameClockDomains(padding_inserter, "eth_tx")
-            self.submodules += RenameClockDomains(padding_checker, "eth_rx")
+            self.submodules += ClockDomainsRenamer("eth_tx")(padding_inserter)
+            self.submodules += ClockDomainsRenamer("eth_rx")(padding_checker)
 
             tx_pipeline += [padding_inserter]
             rx_pipeline += [padding_checker]
@@ -59,8 +57,8 @@ def __init__(self, phy, dw, endianness="big",
         if dw != 8:
             tx_last_be = last_be.LiteEthMACTXLastBE(phy.dw)
             rx_last_be = last_be.LiteEthMACRXLastBE(phy.dw)
-            self.submodules += RenameClockDomains(tx_last_be, "eth_tx")
-            self.submodules += RenameClockDomains(rx_last_be, "eth_rx")
+            self.submodules += ClockDomainsRenamer("eth_tx")(tx_last_be)
+            self.submodules += ClockDomainsRenamer("eth_rx")(rx_last_be)
 
             tx_pipeline += [tx_last_be]
             rx_pipeline += [rx_last_be]
@@ -74,8 +72,8 @@ def __init__(self, phy, dw, endianness="big",
             rx_converter = Converter(eth_phy_description(phy.dw),
                                      eth_phy_description(dw),
                                      reverse=reverse)
-            self.submodules += RenameClockDomains(tx_converter, "eth_tx")
-            self.submodules += RenameClockDomains(rx_converter, "eth_rx")
+            self.submodules += ClockDomainsRenamer("eth_tx")(tx_converter)
+            self.submodules += ClockDomainsRenamer("eth_rx")(rx_converter)
 
             tx_pipeline += [tx_converter]
             rx_pipeline += [rx_converter]
@@ -87,14 +85,16 @@ def __init__(self, phy, dw, endianness="big",
             fifo_depth = 64
         tx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
         rx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
-        self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
-        self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
+        self.submodules += ClockDomainsRenamer({"write": "sys", "read": "eth_tx"})(tx_cdc)
+        self.submodules += ClockDomainsRenamer({"write": "eth_rx", "read": "sys"})(rx_cdc)
 
         tx_pipeline += [tx_cdc]
         rx_pipeline += [rx_cdc]
 
-        # Graph
-        self.submodules.tx_pipeline = Pipeline(*reversed(tx_pipeline))
-        self.submodules.rx_pipeline = Pipeline(*rx_pipeline)
-
-        self.sink, self.source = self.tx_pipeline.sink, self.rx_pipeline.source
+        tx_pipeline_r = list(reversed(tx_pipeline))
+        for s, d in zip(tx_pipeline_r, tx_pipeline_r[1:]):
+            self.comb += s.source.connect(d.sink)
+        for s, d in zip(rx_pipeline, rx_pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+        self.sink = tx_pipeline[-1].sink
+        self.source = rx_pipeline[-1].source
diff --git a/misoclib/com/liteethmini/mac/core/crc.py → misoc/cores/liteeth_mini/mac/core/crc.py b/misoclib/com/liteethmini/mac/core/crc.py → misoc/cores/liteeth_mini/mac/core/crc.py
@@ -1,4 +1,11 @@
-from misoclib.com.liteethmini.common import *
+from collections import OrderedDict
+from functools import reduce
+from operator import xor
+
+from migen import *
+from migen.genlib.misc import chooser
+
+from misoc.interconnect.stream import *
 
 
 class LiteEthMACCRCEngine(Module):
@@ -67,11 +74,11 @@ def _optimize_eq(l):
                     xors += [self.last[n]]
                 elif t == "din":
                     xors += [self.data[n]]
-            self.comb += self.next[i].eq(optree("^", xors))
+            self.comb += self.next[i].eq(reduce(xor, xors))
 
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class LiteEthMACCRC32(Module):
     """IEEE 802.3 CRC
 
@@ -138,7 +145,7 @@ def __init__(self, crc_class, description):
 
         # # #
 
-        dw = flen(sink.data)
+        dw = len(sink.data)
         crc = crc_class(dw)
         fsm = FSM(reset_state="IDLE")
         self.submodules += crc, fsm
@@ -219,13 +226,12 @@ def __init__(self, crc_class, description):
 
         # # #
 
-        dw = flen(sink.data)
+        dw = len(sink.data)
         crc = crc_class(dw)
         self.submodules += crc
         ratio = crc.width//dw
 
-        error = Signal()
-        fifo = InsertReset(SyncFIFO(description, ratio + 1))
+        fifo = ResetInserter()(SyncFIFO(description, ratio + 1))
         self.submodules += fifo
 
         fsm = FSM(reset_state="RESET")

diff --git a/misoclib/com/liteethmini/mac/core/gap.py → misoc/cores/liteeth_mini/mac/core/gap.py b/misoclib/com/liteethmini/mac/core/gap.py → misoc/cores/liteeth_mini/mac/core/gap.py
@@ -1,4 +1,11 @@
-from misoclib.com.liteethmini.common import *
+import math
+
+from migen import *
+from migen.genlib.fsm import *
+
+from misoc.interconnect.stream import Sink, Source
+from misoc.cores.liteeth_mini.common import eth_phy_description, eth_interpacket_gap
+
 
 class LiteEthMACGap(Module):
     def __init__(self, dw, ack_on_gap=False):
@@ -8,20 +15,28 @@ def __init__(self, dw, ack_on_gap=False):
         # # #
 
         gap = math.ceil(eth_interpacket_gap/(dw//8))
-        self.submodules.counter = counter = Counter(max=gap)
+        counter = Signal(max=gap)
+        counter_reset = Signal()
+        counter_ce = Signal()
+        self.sync += \
+            If(counter_reset,
+               counter.eq(0)
+            ).Elif(counter_ce,
+                counter.eq(counter + 1)
+            )
 
         self.submodules.fsm = fsm = FSM(reset_state="COPY")
         fsm.act("COPY",
-            counter.reset.eq(1),
+            counter_reset.eq(1),
             Record.connect(sink, source),
             If(sink.stb & sink.eop & sink.ack,
                 NextState("GAP")
             )
         )
         fsm.act("GAP",
-            counter.ce.eq(1),
+            counter_ce.eq(1),
             sink.ack.eq(int(ack_on_gap)),
-            If(counter.value == (gap-1),
+            If(counter == (gap-1),
                 NextState("COPY")
             )
         )
diff --git a/misoclib/com/liteethmini/mac/core/last_be.py → misoc/cores/liteeth_mini/mac/core/last_be.py b/misoclib/com/liteethmini/mac/core/last_be.py → misoc/cores/liteeth_mini/mac/core/last_be.py
@@ -1,4 +1,7 @@
-from misoclib.com.liteethmini.common import *
+from migen import *
+
+from misoc.interconnect.stream import *
+from misoc.cores.liteeth_mini.common import eth_phy_description
 
 
 class LiteEthMACTXLastBE(Module):

diff --git a/misoclib/com/liteethmini/mac/core/padding.py → misoc/cores/liteeth_mini/mac/core/padding.py b/misoclib/com/liteethmini/mac/core/padding.py → misoc/cores/liteeth_mini/mac/core/padding.py
@@ -1,4 +1,9 @@
-from misoclib.com.liteethmini.common import *
+import math
+
+from migen import *
+
+from misoc.interconnect.stream import *
+from misoc.cores.liteeth_mini.common import eth_phy_description
 
 
 class LiteEthMACPaddingInserter(Module):
@@ -10,19 +15,26 @@ def __init__(self, dw, padding):
 
         padding_limit = math.ceil(padding/(dw/8))-1
 
-        self.submodules.counter = counter = Counter(16, reset=1)
+        counter = Signal(16, reset=1)
         counter_done = Signal()
+        counter_reset = Signal()
+        counter_ce = Signal()
+        self.sync += If(counter_reset,
+                            counter.eq(1)
+                        ).Elif(counter_ce,
+                            counter.eq(counter + 1)
+                        )
         self.comb += [
-            counter.reset.eq(sink.stb & sink.sop & sink.ack),
-            counter.ce.eq(source.stb & source.ack),
-            counter_done.eq(counter.value >= padding_limit),
+            counter_reset.eq(sink.stb & sink.sop & sink.ack),
+            counter_ce.eq(source.stb & source.ack),
+            counter_done.eq(counter >= padding_limit),
         ]
 
         self.submodules.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
             Record.connect(sink, source),
             If(source.stb & source.ack,
-                counter.ce.eq(1),
+                counter_ce.eq(1),
                 If(sink.eop,
                     If(~counter_done,
                         source.eop.eq(0),
@@ -50,7 +62,7 @@ def __init__(self, dw, packet_min_length):
 
         # # #
 
-        # XXX see if we should drop the packet when
+        # TODO: see if we should drop the packet when
         # payload size < minimum ethernet payload size
         self.comb += Record.connect(sink, source)
 
diff --git a/...clib/com/liteethmini/mac/core/preamble.py → ...c/cores/liteeth_mini/mac/core/preamble.py b/...clib/com/liteethmini/mac/core/preamble.py → ...c/cores/liteeth_mini/mac/core/preamble.py
@@ -1,4 +1,10 @@
-from misoclib.com.liteethmini.common import *
+from migen import *
+from migen.genlib.fsm import *
+from migen.genlib.misc import chooser
+from migen.genlib.record import Record
+
+from misoc.interconnect.stream import *
+from misoc.cores.liteeth_mini.common import eth_phy_description, eth_preamble
 
 
 class LiteEthMACPreambleInserter(Module):

diff --git a/misoclib/mem/sdram/phy/__init__.py → ...res/liteeth_mini/mac/frontend/__init__.py b/misoclib/mem/sdram/phy/__init__.py → ...res/liteeth_mini/mac/frontend/__init__.py
diff --git a/...clib/com/liteethmini/mac/frontend/sram.py → ...c/cores/liteeth_mini/mac/frontend/sram.py b/...clib/com/liteethmini/mac/frontend/sram.py → ...c/cores/liteeth_mini/mac/frontend/sram.py
@@ -1,7 +1,10 @@
-from misoclib.com.liteethmini.common import *
+from misoc import *
 
-from migen.bank.description import *
-from migen.bank.eventmanager import *
+from misoc.interconnect.csr import *
+from misoc.interconnect.csr_eventmanager import *
+from misoc.interconnect.stream import *
+
+from misoc.cores.liteeth_mini.common import eth_phy_description
 
 
 class LiteEthMACSRAMWriter(Module, AutoCSR):
@@ -36,12 +39,19 @@ def __init__(self, dw, depth, nslots=2):
             ).Else(
                 increment.eq(4)
             )
-        counter = Counter(lengthbits, increment=increment)
-        self.submodules += counter
+        counter = Signal(lengthbits)
+        counter_reset = Signal()
+        counter_ce = Signal()
+        self.sync += If(counter_reset,
+                        counter.eq(0)
+                    ).Elif(counter_ce,
+                        counter.eq(counter + increment)
+                    )
 
         # slot computation
-        slot = Counter(slotbits)
-        self.submodules += slot
+        slot = Signal(slotbits)
+        slot_ce = Signal()
+        self.sync += If(slot_ce, slot.eq(slot + 1))
 
         ongoing = Signal()
 
@@ -57,13 +67,13 @@ def __init__(self, dw, depth, nslots=2):
             If(sink.stb & sink.sop,
                 If(fifo.sink.ack,
                     ongoing.eq(1),
-                    counter.ce.eq(1),
+                    counter_ce.eq(1),
                     NextState("WRITE")
                 )
             )
         )
         fsm.act("WRITE",
-            counter.ce.eq(sink.stb),
+            counter_ce.eq(sink.stb),
             ongoing.eq(1),
             If(sink.stb & sink.eop,
                 If((sink.error & sink.last_be) != 0,
@@ -74,16 +84,16 @@ def __init__(self, dw, depth, nslots=2):
             )
         )
         fsm.act("DISCARD",
-            counter.reset.eq(1),
+            counter_reset.eq(1),
             NextState("IDLE")
         )
         self.comb += [
-            fifo.sink.slot.eq(slot.value),
-            fifo.sink.length.eq(counter.value)
+            fifo.sink.slot.eq(slot),
+            fifo.sink.length.eq(counter)
         ]
         fsm.act("TERMINATE",
-            counter.reset.eq(1),
-            slot.ce.eq(1),
+            counter_reset.eq(1),
+            slot_ce.eq(1),
             fifo.sink.stb.eq(1),
             NextState("IDLE")
         )
@@ -106,13 +116,13 @@ def __init__(self, dw, depth, nslots=2):
         cases = {}
         for n, port in enumerate(ports):
             cases[n] = [
-                ports[n].adr.eq(counter.value[2:]),
+                ports[n].adr.eq(counter[2:]),
                 ports[n].dat_w.eq(sink.data),
                 If(sink.stb & ongoing,
                     ports[n].we.eq(0xf)
                 )
             ]
-        self.comb += Case(slot.value, cases)
+        self.comb += Case(slot, cases)
 
 
 class LiteEthMACSRAMReader(Module, AutoCSR):
@@ -145,7 +155,15 @@ def __init__(self, dw, depth, nslots=2):
         ]
 
         # length computation
-        self.submodules.counter = counter = Counter(lengthbits, increment=4)
+        counter = Signal(lengthbits)
+        counter_reset = Signal()
+        counter_ce = Signal()
+        self.sync += If(counter_reset,
+                            counter.eq(0)
+                        ).Elif(counter_ce,
+                            counter.eq(counter + 4)
+                        )
+
 
         # fsm
         first = Signal()
@@ -156,7 +174,7 @@ def __init__(self, dw, depth, nslots=2):
         self.submodules += fsm
 
         fsm.act("IDLE",
-            counter.reset.eq(1),
+            counter_reset.eq(1),
             If(fifo.source.stb,
                 NextState("CHECK")
             )
@@ -187,7 +205,7 @@ def __init__(self, dw, depth, nslots=2):
             source.sop.eq(first),
             source.eop.eq(last),
             If(source.ack,
-                counter.ce.eq(~last),
+                counter_ce.eq(~last),
                 NextState("CHECK")
             )
         )
@@ -205,7 +223,7 @@ def __init__(self, dw, depth, nslots=2):
                 first.eq(0)
             )
         ]
-        self.comb += last.eq((counter.value + 4) >= fifo.source.length)
+        self.comb += last.eq((counter + 4) >= fifo.source.length)
         self.sync += last_d.eq(last)
 
         # memory
@@ -221,7 +239,7 @@ def __init__(self, dw, depth, nslots=2):
 
         cases = {}
         for n, port in enumerate(ports):
-            self.comb += ports[n].adr.eq(counter.value[2:])
+            self.comb += ports[n].adr.eq(counter[2:])
             cases[n] = [source.data.eq(port.dat_r)]
         self.comb += Case(rd_slot, cases)
 

diff --git a/.../com/liteethmini/mac/frontend/wishbone.py → ...res/liteeth_mini/mac/frontend/wishbone.py b/.../com/liteethmini/mac/frontend/wishbone.py → ...res/liteeth_mini/mac/frontend/wishbone.py
@@ -1,9 +1,12 @@
-from misoclib.com.liteethmini.common import *
-from misoclib.com.liteethmini.mac.frontend import sram
-
-from migen.bus import wishbone
+from migen import *
 from migen.fhdl.simplify import FullMemoryWE
 
+from misoc.interconnect import wishbone
+from misoc.interconnect.csr import *
+from misoc.interconnect.stream import *
+from misoc.cores.liteeth_mini.common import eth_phy_description, buffer_depth
+from misoc.cores.liteeth_mini.mac.frontend import sram
+
 
 class LiteEthMACWishboneInterface(Module, AutoCSR):
     def __init__(self, dw, nrxslots=2, ntxslots=2):

diff --git a/misoclib/com/liteethmini/phy/__init__.py → misoc/cores/liteeth_mini/phy/__init__.py b/misoclib/com/liteethmini/phy/__init__.py → misoc/cores/liteeth_mini/phy/__init__.py
@@ -1,27 +1,23 @@
-from misoclib.com.liteethmini.common import *
+from misoc.cores.liteeth_mini.common import *
 
 
 def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
     # Autodetect PHY
-    if hasattr(pads, "source_stb"):
-        # This is a simulation PHY
-        from misoclib.com.liteethmini.phy.sim import LiteEthPHYSim
-        return LiteEthPHYSim(pads)
-    elif hasattr(clock_pads, "gtx") and flen(pads.tx_data) == 8:
+    if hasattr(clock_pads, "gtx") and len(pads.tx_data) == 8:
         if hasattr(clock_pads, "tx"):
             # This is a 10/100/1G PHY
-            from misoclib.com.liteethmini.phy.gmii_mii import LiteEthPHYGMIIMII
+            from misoc.cores.liteeth_mini.phy.gmii_mii import LiteEthPHYGMIIMII
             return LiteEthPHYGMIIMII(clock_pads, pads, clk_freq=clk_freq, **kwargs)
         else:
             # This is a pure 1G PHY
-            from misoclib.com.liteethmini.phy.gmii import LiteEthPHYGMII
+            from misoc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMII
             return LiteEthPHYGMII(clock_pads, pads, **kwargs)
     elif hasattr(pads, "rx_ctl"):
         # This is a 10/100/1G RGMII PHY
         raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation")
-    elif flen(pads.tx_data) == 4:
+    elif len(pads.tx_data) == 4:
         # This is a MII PHY
-        from misoclib.com.liteethmini.phy.mii import LiteEthPHYMII
+        from misoc.cores.liteeth_mini.phy.mii import LiteEthPHYMII
         return LiteEthPHYMII(clock_pads, pads, **kwargs)
     else:
         raise ValueError("Unable to autodetect PHY from platform file, use direct instantiation")
diff --git a/misoclib/com/liteethmini/phy/gmii.py → misoc/cores/liteeth_mini/phy/gmii.py b/misoclib/com/liteethmini/phy/gmii.py → misoc/cores/liteeth_mini/phy/gmii.py
@@ -1,6 +1,8 @@
+from migen import *
 from migen.genlib.io import DDROutput
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from misoclib.com.liteethmini.common import *
+from misoc.cores.liteeth_mini.common import *
 
 
 class LiteEthPHYGMIITX(Module):
@@ -69,11 +71,13 @@ def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
 
         if with_hw_init_reset:
             reset = Signal()
+            counter = Signal(max=512)
             counter_done = Signal()
-            self.submodules.counter = counter = Counter(max=512)
+            counter_ce = Signal()
+            self.sync += If(counter_ce, counter.eq(counter + 1))
             self.comb += [
-                counter_done.eq(counter.value == 256),
-                counter.ce.eq(~counter_done),
+                counter_done.eq(counter == 256),
+                counter_ce.eq(~counter_done),
                 reset.eq(~counter_done | self._reset.storage)
             ]
         else:
@@ -88,11 +92,7 @@ def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
 class LiteEthPHYGMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
-        self.submodules.crg = LiteEthPHYGMIICRG(clock_pads,
-                                                pads,
-                                                with_hw_init_reset)
-        self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads),
-                                                "eth_tx")
-        self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads),
-                                                "eth_rx")
+        self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
+        self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))
+        self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads))
         self.sink, self.source = self.tx.sink, self.rx.source
diff --git a/misoclib/com/liteethmini/phy/gmii_mii.py → misoc/cores/liteeth_mini/phy/gmii_mii.py b/misoclib/com/liteethmini/phy/gmii_mii.py → misoc/cores/liteeth_mini/phy/gmii_mii.py
@@ -1,12 +1,13 @@
+from migen import *
 from migen.genlib.io import DDROutput
-from migen.flow.plumbing import Multiplexer, Demultiplexer
 from migen.genlib.cdc import PulseSynchronizer
 
-from misoclib.com.liteethmini.common import *
+from misoc.interconnect.stream import *
+from misoc.cores.liteeth_mini.common import *
+from misoc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMIICRG
+from misoc.cores.liteeth_mini.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
+from misoc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
 
-from misoclib.com.liteethmini.phy.gmii import LiteEthPHYGMIICRG
-from misoclib.com.liteethmini.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
-from misoclib.com.liteethmini.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
 
 modes = {
     "GMII": 0,
@@ -118,28 +119,36 @@ def __init__(self, clk_freq):
         self.submodules += eth_ps
 
         # sys_clk domain counter
-        sys_counter = Counter(24)
-        self.submodules += sys_counter
+        sys_counter = Signal(24)
+        sys_counter_reset = Signal()
+        sys_counter_ce = Signal()
+        self.sync += [
+            If(sys_counter_reset,
+               sys_counter.eq(0)
+            ).Elif(sys_counter_ce,
+                sys_counter.eq(sys_counter + 1)
+            )
+        ]
 
         fsm = FSM(reset_state="IDLE")
         self.submodules += fsm
 
         fsm.act("IDLE",
-            sys_counter.reset.eq(1),
+            sys_counter_reset.eq(1),
             If(sys_tick,
                 NextState("COUNT")
             )
         )
         fsm.act("COUNT",
-            sys_counter.ce.eq(1),
+            sys_counter_ce.eq(1),
             If(sys_tick,
                 NextState("DETECTION")
             )
         )
         fsm.act("DETECTION",
             update_mode.eq(1),
             # if freq < 125MHz-5% use MII mode
-            If(sys_counter.value > int((clk_freq/125000000)*1024*1.05),
+            If(sys_counter > int((clk_freq/125000000)*1024*1.05),
                 mode.eq(1)
             # if freq >= 125MHz-5% use GMII mode
             ).Else(
@@ -156,6 +165,6 @@ def __init__(self, clock_pads, pads, clk_freq, with_hw_init_reset=True):
         self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq)
         mode = self.mode_detection.mode
         self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, mode == modes["MII"])
-        self.submodules.tx = RenameClockDomains(LiteEthPHYGMIIMIITX(pads, mode), "eth_tx")
-        self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIMIIRX(pads, mode), "eth_rx")
+        self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIIMIITX(pads, mode))
+        self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIMIIRX(pads, mode))
         self.sink, self.source = self.tx.sink, self.rx.source
diff --git a/misoclib/com/liteethmini/phy/loopback.py → misoc/cores/liteeth_mini/phy/loopback.py b/misoclib/com/liteethmini/phy/loopback.py → misoc/cores/liteeth_mini/phy/loopback.py
@@ -1,5 +1,9 @@
-from misoclib.com.liteethmini.common import *
-from misoclib.com.liteethmini.generic import *
+from migen import *
+
+from misoc.interconnect.csr import *
+from misoc.interconnect.stream import *
+from misoc.cores.liteeth_mini.common import *
+from misoc.cores.liteeth.mini.generic import *
 
 
 class LiteEthPHYLoopbackCRG(Module, AutoCSR):
@@ -26,6 +30,6 @@ class LiteEthPHYLoopback(Module, AutoCSR):
     def __init__(self):
         self.dw = 8
         self.submodules.crg = LiteEthLoopbackPHYCRG()
-        self.sink = sink = Sink(eth_phy_description(8))
-        self.source = source = Source(eth_phy_description(8))
+        self.sink = Sink(eth_phy_description(8))
+        self.source = Source(eth_phy_description(8))
         self.comb += Record.connect(self.sink, self.source)
diff --git a/misoclib/com/liteethmini/phy/mii.py → misoc/cores/liteeth_mini/phy/mii.py b/misoclib/com/liteethmini/phy/mii.py → misoc/cores/liteeth_mini/phy/mii.py
@@ -1,4 +1,8 @@
-from misoclib.com.liteethmini.common import *
+from migen import *
+
+from misoc.interconnect.csr import *
+from misoc.interconnect.stream import *
+from misoc.cores.liteeth_mini.common import *
 
 
 def converter_description(dw):
@@ -46,7 +50,7 @@ def __init__(self, pads):
 
         converter = Converter(converter_description(4),
                               converter_description(8))
-        converter = InsertReset(converter)
+        converter = ResetInserter()(converter)
         self.submodules += converter
 
         self.sync += [
@@ -101,6 +105,6 @@ class LiteEthPHYMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
         self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
-        self.submodules.tx = RenameClockDomains(LiteEthPHYMIITX(pads), "eth_tx")
-        self.submodules.rx = RenameClockDomains(LiteEthPHYMIIRX(pads), "eth_rx")
+        self.submodules.tx =  ClockDomainsRenamer("eth_tx")(LiteEthPHYMIITX(pads))
+        self.submodules.rx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIIRX(pads))
         self.sink, self.source = self.tx.sink, self.rx.source
diff --git a/misoclib/com/liteethmini/phy/s6rgmii.py → misoc/cores/liteeth_mini/phy/s6rgmii.py b/misoclib/com/liteethmini/phy/s6rgmii.py → misoc/cores/liteeth_mini/phy/s6rgmii.py
@@ -1,10 +1,13 @@
 # RGMII PHY for Spartan-6
 
+from migen import *
 from migen.genlib.io import DDROutput
 from migen.genlib.misc import WaitTimer
 from migen.genlib.fsm import FSM, NextState
 
-from misoclib.com.liteethmini.common import *
+from misoc.interconnect.stream import *
+from misoc.interconnect.csr import *
+from misoc.cores.liteeth_mini.common import *
 
 
 class LiteEthPHYRGMIITX(Module):
@@ -152,11 +155,7 @@ def __init__(self, clock_pads, pads, with_hw_init_reset):
 class LiteEthPHYRGMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
-        self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads,
-                                                 pads,
-                                                 with_hw_init_reset)
-        self.submodules.tx = RenameClockDomains(LiteEthPHYRGMIITX(pads),
-                                                "eth_tx")
-        self.submodules.rx = RenameClockDomains(LiteEthPHYRGMIIRX(pads),
-                                                "eth_rx")
+        self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset)
+        self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
+        self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
         self.sink, self.source = self.tx.sink, self.rx.source
diff --git a/misoc/cores/lm32/__init__.py b/misoc/cores/lm32/__init__.py
@@ -0,0 +1 @@
+from misoc.cores.lm32.core import LM32
diff --git a/misoclib/cpu/lm32.py → misoc/cores/lm32/core.py b/misoclib/cpu/lm32.py → misoc/cores/lm32/core.py
@@ -1,7 +1,8 @@
 import os
 
-from migen.fhdl.std import *
-from migen.bus import wishbone
+from migen import *
+
+from misoc.interconnect import wishbone
 
 
 class LM32(Module):
@@ -54,10 +55,12 @@ def __init__(self, platform, eba_reset):
         ]
 
         # add Verilog sources
-        platform.add_sources(os.path.join("extcores", "lm32", "submodule", "rtl"),
+        vdir = os.path.join(
+            os.path.abspath(os.path.dirname(__file__)), "verilog")
+        platform.add_sources(os.path.join(vdir, "submodule", "rtl"),
                 "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
                 "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
                 "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
                 "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
                 "lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
-        platform.add_verilog_include_path(os.path.join("extcores", "lm32"))
+        platform.add_verilog_include_path(vdir)
diff --git a/extcores/lm32/lm32_config.v → misoc/cores/lm32/verilog/lm32_config.v b/extcores/lm32/lm32_config.v → misoc/cores/lm32/verilog/lm32_config.v
diff --git a/extcores/lm32/submodule → misoc/cores/lm32/verilog/submodule b/extcores/lm32/submodule → misoc/cores/lm32/verilog/submodule
diff --git a/misoc/cores/minicon/__init__.py b/misoc/cores/minicon/__init__.py
@@ -0,0 +1 @@
+from misoc.cores.minicon.core import Minicon
diff --git a/misoclib/mem/sdram/core/minicon/__init__.py → misoc/cores/minicon/core.py b/misoclib/mem/sdram/core/minicon/__init__.py → misoc/cores/minicon/core.py
@@ -1,9 +1,12 @@
-from migen.fhdl.std import *
-from migen.bus import wishbone
+from functools import reduce
+from operator import or_
+
+from migen import *
 from migen.genlib.fsm import FSM, NextState
-from migen.genlib.misc import optree, WaitTimer
+from migen.genlib.misc import WaitTimer
 
-from misoclib.mem.sdram.phy import dfi as dfibus
+from misoc.interconnect import dfi as dfibus
+from misoc.interconnect import wishbone
 
 
 class _AddressSlicer:
@@ -36,8 +39,8 @@ def col(self, address):
             return Cat(Replicate(0, self.address_align), address[:split])
 
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class _Bank(Module):
     def __init__(self, geom_settings):
         self.open = Signal()
@@ -57,11 +60,6 @@ def __init__(self, geom_settings):
         self.comb += self.hit.eq(~self.idle & (self.row == row))
 
 
-class MiniconSettings:
-    def __init__(self, l2_size=0):
-        self.l2_size = l2_size
-
-
 class Minicon(Module):
     def __init__(self, phy_settings, geom_settings, timing_settings):
         if phy_settings.memtype in ["SDR"]:
@@ -96,7 +94,6 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
                                 address_align)
 
         # Manage banks
-        bank_open = Signal()
         bank_idle = Signal()
         bank_hit = Signal()
 
@@ -117,8 +114,8 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
         self.comb += Case(slicer.bank(bus.adr), cases)
 
         self.comb += [
-            bank_hit.eq(optree("|", [bank.hit & bank.ce for bank in banks])),
-            bank_idle.eq(optree("|", [bank.idle & bank.ce for bank in banks])),
+            bank_hit.eq(reduce(or_, [bank.hit & bank.ce for bank in banks])),
+            bank_idle.eq(reduce(or_, [bank.idle & bank.ce for bank in banks])),
         ]
 
         # Timings

diff --git a/misoclib/mem/sdram/test/minicon_tb.py → misoc/cores/minicon/test.py b/misoclib/mem/sdram/test/minicon_tb.py → misoc/cores/minicon/test.py
@@ -1,12 +1,12 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus.transactions import TRead, TWrite
 from migen.bus import wishbone
 from migen.sim.generic import Simulator
 from migen.sim import icarus
 from mibuild.platforms import papilio_pro as board
-from misoclib import sdram
-from misoclib.mem.sdram.core.minicon import Minicon
-from misoclib.mem.sdram.phy import gensdrphy
+from misoc import sdram
+from misoc.mem.sdram.core.minicon import Minicon
+from misoc.mem.sdram.phy import gensdrphy
 from itertools import chain
 from os.path import isfile
 import sys
@@ -32,7 +32,7 @@ def __init__(self, sdrphy, dfi, sdram_geom, sdram_timing, pads, sdram_clk):
         self.submodules.slave = Minicon(phy_settings, sdram_geom, sdram_timing)
 
         self.submodules.tap = wishbone.Tap(self.slave.bus)
-        self.submodules.dc = dc = wishbone.DownConverter(32, phy_settings.nphases*flen(dfi.phases[rdphase].rddata))
+        self.submodules.dc = dc = wishbone.DownConverter(32, phy_settings.nphases*len(dfi.phases[rdphase].rddata))
         self.submodules.master = wishbone.Initiator(self.genxfers(), bus=dc.wishbone_i)
         self.submodules.intercon = wishbone.InterconnectPointToPoint(dc.wishbone_o, self.slave.bus)
 

diff --git a/misoc/cores/mor1kx/__init__.py b/misoc/cores/mor1kx/__init__.py
@@ -0,0 +1 @@
+from misoc.cores.mor1kx.core import MOR1KX
diff --git a/misoclib/cpu/mor1kx.py → misoc/cores/mor1kx/core.py b/misoclib/cpu/mor1kx.py → misoc/cores/mor1kx/core.py
@@ -1,7 +1,8 @@
 import os
 
-from migen.fhdl.std import *
-from migen.bus import wishbone
+from migen import *
+
+from misoc.interconnect import wishbone
 
 
 class MOR1KX(Module):
@@ -76,5 +77,7 @@ def __init__(self, platform, reset_pc):
         ]
 
         # add Verilog sources
-        platform.add_source_dir(os.path.join("extcores", "mor1kx", "submodule",
-                                             "rtl", "verilog"))
+        vdir = os.path.join(
+            os.path.abspath(os.path.dirname(__file__)),
+            "verilog", "rtl", "verilog")
+        platform.add_source_dir(vdir)
diff --git a/misoc/cores/mor1kx/verilog b/misoc/cores/mor1kx/verilog
diff --git a/misoclib/mxcrg.v → misoc/cores/mxcrg.v b/misoclib/mxcrg.v → misoc/cores/mxcrg.v
diff --git a/misoclib/mem/flash/norflash16.py → misoc/cores/nor_flash_16.py b/misoclib/mem/flash/norflash16.py → misoc/cores/nor_flash_16.py
@@ -1,7 +1,8 @@
-from migen.fhdl.std import *
-from migen.bus import wishbone
+from migen import *
 from migen.genlib.fsm import FSM, NextState
 
+from misoc.interconnect import wishbone
+
 
 class NorFlash16(Module):
     def __init__(self, pads, rd_timing, wr_timing):

diff --git a/misoclib/mem/sdram/phy/simphy.py → misoc/cores/sdram_model.py b/misoclib/mem/sdram/phy/simphy.py → misoc/cores/sdram_model.py
@@ -6,10 +6,10 @@
 # TODO:
 # - add $display support to Migen and manage timing violations?
 
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl.specials import *
-from misoclib.mem.sdram.phy.dfi import *
-from misoclib.mem import sdram
+from misoc.mem.sdram.phy.dfi import *
+from misoc.mem import sdram
 
 
 class Bank(Module):
@@ -158,7 +158,6 @@ def __init__(self, module, settings):
 
             # bank reads
             reads = Signal(len(phases))
-            read_data = Signal(data_width)
             cases = {}
             for np, phase in enumerate(phases):
                 self.comb += reads[np].eq(phase.read)

diff --git a/misoc/cores/sdram_phy/__init__.py b/misoc/cores/sdram_phy/__init__.py
@@ -0,0 +1,3 @@
+from misoc.cores.sdram_phy.gensdrphy import GENSDRPHY
+from misoc.cores.sdram_phy.s6ddrphy import S6HalfRateDDRPHY, S6QuarterRateDDRPHY
+from misoc.cores.sdram_phy.k7ddrphy import K7DDRPHY
diff --git a/misoclib/mem/sdram/phy/gensdrphy.py → misoc/cores/sdram_phy/gensdrphy.py b/misoclib/mem/sdram/phy/gensdrphy.py → misoc/cores/sdram_phy/gensdrphy.py
@@ -21,22 +21,22 @@
 # This PHY only supports CAS Latency 2.
 #
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
-from migen.fhdl.specials import *
+from migen.fhdl.specials import Tristate
 
-from misoclib.mem.sdram.phy.dfi import *
-from misoclib.mem import sdram
+from misoc.interconnect.dfi import *
+from misoc.cores import sdram_settings
 
 
 class GENSDRPHY(Module):
-    def __init__(self, pads, module):
-        addressbits = flen(pads.a)
-        bankbits = flen(pads.ba)
-        databits = flen(pads.dq)
+    def __init__(self, pads):
+        addressbits = len(pads.a)
+        bankbits = len(pads.ba)
+        databits = len(pads.dq)
 
-        self.settings = sdram.PhySettings(
-            memtype=module.memtype,
+        self.settings = sdram_settings.PhySettings(
+            memtype="SDR",
             dfi_databits=databits,
             nphases=1,
             rdphase=0,
@@ -47,7 +47,6 @@ def __init__(self, pads, module):
             read_latency=4,
             write_latency=0
         )
-        self.module = module
 
         self.dfi = Interface(addressbits, bankbits, databits)
 

diff --git a/misoclib/mem/sdram/phy/k7ddrphy.py → misoc/cores/sdram_phy/k7ddrphy.py b/misoclib/mem/sdram/phy/k7ddrphy.py → misoc/cores/sdram_phy/k7ddrphy.py
@@ -1,17 +1,17 @@
 # tCK=5ns CL=7 CWL=6
 
-from migen.fhdl.std import *
-from migen.bank.description import *
+from migen import *
 
-from misoclib.mem.sdram.phy.dfi import *
-from misoclib.mem import sdram
+from misoc.interconnect.dfi import *
+from misoc.interconnect.csr import *
+from misoc.cores import sdram_settings
 
 
 class K7DDRPHY(Module, AutoCSR):
-    def __init__(self, pads, module):
-        addressbits = flen(pads.a)
-        bankbits = flen(pads.ba)
-        databits = flen(pads.dq)
+    def __init__(self, pads):
+        addressbits = len(pads.a)
+        bankbits = len(pads.ba)
+        databits = len(pads.dq)
         nphases = 4
 
         self._wlevel_en = CSRStorage()
@@ -25,8 +25,8 @@ def __init__(self, pads, module):
         self._wdly_dqs_rst = CSR()
         self._wdly_dqs_inc = CSR()
 
-        self.settings = sdram.PhySettings(
-            memtype=module.memtype,
+        self.settings = sdram_settings.PhySettings(
+            memtype="DDR3",
             dfi_databits=2*databits,
             nphases=nphases,
             rdphase=0,
@@ -38,7 +38,6 @@ def __init__(self, pads, module):
             read_latency=6,
             write_latency=2
         )
-        self.module = module
 
         self.dfi = Interface(addressbits, bankbits, 2*databits, nphases)
 

diff --git a/misoclib/mem/sdram/phy/s6ddrphy.py → misoc/cores/sdram_phy/s6ddrphy.py b/misoclib/mem/sdram/phy/s6ddrphy.py → misoc/cores/sdram_phy/s6ddrphy.py
@@ -16,24 +16,27 @@
 # Write commands must be sent on phase 1.
 #
 
-from migen.fhdl.std import *
+from functools import reduce
+from operator import or_
+
+from migen import *
 from migen.genlib.record import *
 
-from misoclib.mem.sdram.phy.dfi import *
-from misoclib.mem import sdram
+from misoc.interconnect.dfi import *
+from misoc.cores import sdram_settings
 
 
 class S6HalfRateDDRPHY(Module):
-    def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
-        if module.memtype not in ["DDR", "LPDDR", "DDR2", "DDR3"]:
+    def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
+        if memtype not in ["DDR", "LPDDR", "DDR2", "DDR3"]:
             raise NotImplementedError("S6HalfRateDDRPHY only supports DDR, LPDDR, DDR2 and DDR3")
-        addressbits = flen(pads.a)
-        bankbits = flen(pads.ba)
-        databits = flen(pads.dq)
+        addressbits = len(pads.a)
+        bankbits = len(pads.ba)
+        databits = len(pads.dq)
         nphases = 2
 
-        if module.memtype == "DDR3":
-            self.settings = sdram.PhySettings(
+        if memtype == "DDR3":
+            self.settings = sdram_settings.PhySettings(
                 memtype="DDR3",
                 dfi_databits=2*databits,
                 nphases=nphases,
@@ -47,8 +50,8 @@ def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
                 write_latency=2
             )
         else:
-            self.settings = sdram.PhySettings(
-                memtype=module.memtype,
+            self.settings = sdram_settings.PhySettings(
+                memtype=memtype,
                 dfi_databits=2*databits,
                 nphases=nphases,
                 rdphase=0,
@@ -60,8 +63,6 @@ def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
                 write_latency=0
             )
 
-        self.module = module
-
         self.dfi = Interface(addressbits, bankbits, 2*databits, nphases)
         self.clk4x_wr_strb = Signal()
         self.clk4x_rd_strb = Signal()
@@ -361,9 +362,9 @@ def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
 
         # write
         wrdata_en = Signal()
-        self.comb += wrdata_en.eq(optree("|", [d_dfi[p].wrdata_en for p in range(nphases)]))
+        self.comb += wrdata_en.eq(reduce(or_, [d_dfi[p].wrdata_en for p in range(nphases)]))
 
-        if module.memtype == "DDR3":
+        if memtype == "DDR3":
             r_drive_dq = Signal(self.settings.cwl-1)
             sd_sdram_half += r_drive_dq.eq(Cat(wrdata_en, r_drive_dq))
             self.comb += drive_dq.eq(r_drive_dq[self.settings.cwl-2])
@@ -376,14 +377,14 @@ def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
         r_dfi_wrdata_en = Signal(max(self.settings.cwl, self.settings.cl))
         sd_sdram_half += r_dfi_wrdata_en.eq(Cat(wrdata_en_d, r_dfi_wrdata_en))
 
-        if module.memtype == "DDR3":
+        if memtype == "DDR3":
             self.comb += drive_dqs.eq(r_dfi_wrdata_en[self.settings.cwl-1])
         else:
             self.comb += drive_dqs.eq(r_dfi_wrdata_en[1])
 
         # read
         rddata_en = Signal()
-        self.comb += rddata_en.eq(optree("|", [d_dfi[p].rddata_en for p in range(nphases)]))
+        self.comb += rddata_en.eq(reduce(or_, [d_dfi[p].rddata_en for p in range(nphases)]))
 
         rddata_sr = Signal(self.settings.read_latency)
         sd_sys += rddata_sr.eq(Cat(rddata_sr[1:self.settings.read_latency], rddata_en))
@@ -396,18 +397,16 @@ def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
 
 
 class S6QuarterRateDDRPHY(Module):
-    def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
-        if module.memtype not in ["DDR3"]:
-            raise NotImplementedError("S6QuarterRateDDRPHY only supports DDR3")
-        half_rate_phy = S6HalfRateDDRPHY(pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment)
+    def __init__(self, pads, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
+        half_rate_phy = S6HalfRateDDRPHY(pads, "DDR3", rd_bitslip, wr_bitslip, dqs_ddr_alignment)
         self.submodules += RenameClockDomains(half_rate_phy, {"sys" : "sys2x"})
 
-        addressbits = flen(pads.a)
-        bankbits = flen(pads.ba)
-        databits = flen(pads.dq)
+        addressbits = len(pads.a)
+        bankbits = len(pads.ba)
+        databits = len(pads.dq)
         nphases = 4
 
-        self.settings = sdram.PhySettings(
+        self.settings = sdram_settings.PhySettings(
             memtype="DDR3",
             dfi_databits=2*databits,
             nphases=nphases,
@@ -421,8 +420,6 @@ def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
             write_latency=2//2
         )
 
-        self.module = module
-
         self.dfi = Interface(addressbits, bankbits, 2*databits, nphases)
         self.clk8x_wr_strb = half_rate_phy.clk4x_wr_strb
         self.clk8x_rd_strb = half_rate_phy.clk4x_rd_strb

diff --git a/misoclib/mem/sdram/module.py → misoc/cores/sdram_settings.py b/misoclib/mem/sdram/module.py → misoc/cores/sdram_settings.py
@@ -1,9 +1,20 @@
-# SDRAM memory modules library
-#
-# This library avoid duplications of memory modules definitions in targets and
-# ease SDRAM usage. (User can only select an already existing module or create
-# one for its board and contribute to this library)
-#
+from math import ceil
+from collections import namedtuple
+
+from migen import *
+
+
+PhySettingsT = namedtuple("PhySettings", "memtype dfi_databits nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency")
+def PhySettings(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, read_latency, write_latency, cwl=0):
+    return PhySettingsT(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, cwl, read_latency, write_latency)
+
+GeomSettingsT = namedtuple("_GeomSettings", "bankbits rowbits colbits addressbits")
+def GeomSettings(bankbits, rowbits, colbits):
+    return GeomSettingsT(bankbits, rowbits, colbits, max(rowbits, colbits))
+
+TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")
+
+
 # TODO:
 #   Try to share the maximum information we can between modules:
 #    - ex: MT46V32M16 and MT46H32M16 are almost identical (V=DDR, H=LPDDR)
@@ -14,22 +25,17 @@
 #    - Modules can have different speedgrades, add support for it (and also add
 #      a check to verify clk_freq is in the supported range)
 
-from math import ceil
-
-from migen.fhdl.std import *
-from misoclib.mem import sdram
-
 
 class SDRAMModule:
     def __init__(self, clk_freq, memtype, geom_settings, timing_settings):
         self.clk_freq = clk_freq
         self.memtype = memtype
-        self.geom_settings = sdram.GeomSettings(
+        self.geom_settings = GeomSettings(
             bankbits=log2_int(geom_settings["nbanks"]),
             rowbits=log2_int(geom_settings["nrows"]),
             colbits=log2_int(geom_settings["ncols"]),
         )
-        self.timing_settings = sdram.TimingSettings(
+        self.timing_settings = TimingSettings(
             tRP=self.ns(timing_settings["tRP"]),
             tRCD=self.ns(timing_settings["tRCD"]),
             tWR=self.ns(timing_settings["tWR"]),
@@ -52,7 +58,7 @@ class IS42S16160(SDRAMModule):
         "nrows":  8192,
         "ncols":  512
     }
-    # Note: timings for -7 speedgrade (add support for others speedgrades)
+    # Timings for -7 speedgrade
     timing_settings = {
         "tRP":   20,
         "tRCD":  20,
@@ -62,7 +68,7 @@ class IS42S16160(SDRAMModule):
         "tRFC":  70
     }
     def __init__(self, clk_freq):
-        SDRAMModule.__init__(self, clk_freq,  "SDR", self.geom_settings,
+        SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
             self.timing_settings)
 
 
@@ -91,7 +97,7 @@ class AS4C16M16(SDRAMModule):
         "nrows":  8192,
         "ncols":  512
     }
-    # Note: timings for -6 speedgrade (add support for others speedgrades)
+    # Timings for -6 speedgrade
     timing_settings = {
         "tRP":   18,
         "tRCD":  18,
@@ -219,7 +225,6 @@ class MT41J128M16(SDRAMModule):
         "tREFI": 64*1000*1000/16384,
         "tRFC":  260,
     }
-
     def __init__(self, clk_freq):
         SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
             self.timing_settings)
diff --git a/misoclib/mem/sdram/frontend/memtest.py → misoc/cores/sdram_tester.py b/misoclib/mem/sdram/frontend/memtest.py → misoc/cores/sdram_tester.py
@@ -1,13 +1,16 @@
-from migen.fhdl.std import *
-from migen.genlib.misc import optree
-from migen.bank.description import *
-from migen.actorlib.spi import *
+from functools import reduce
+from operator import xor
 
-from misoclib.mem.sdram.frontend import dma_lasmi
+from migen import *
 
+from misoc.interconnect.csr import *
+from misoc.interconnect import dma_lasmi
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+# TODO: implement or replace DMAControllers in MiSoC
+
+
+@ResetInserter()
+@CEInserter()
 class LFSR(Module):
     def __init__(self, n_out, n_state=31, taps=[27, 30]):
         self.o = Signal(n_out)
@@ -18,7 +21,7 @@ def __init__(self, n_out, n_state=31, taps=[27, 30]):
         curval = [state[i] for i in range(n_state)]
         curval += [0]*(n_out - n_state)
         for i in range(n_out):
-            nv = ~optree("^", [curval[tap] for tap in taps])
+            nv = ~reduce(xor, [curval[tap] for tap in taps])
             curval.insert(0, nv)
             curval.pop()
 
@@ -27,10 +30,11 @@ def __init__(self, n_out, n_state=31, taps=[27, 30]):
             self.o.eq(Cat(*curval))
         ]
 
+
 memtest_magic = 0x361f
 
 
-class MemtestWriter(Module):
+class Writer(Module):
     def __init__(self, lasmim):
         self._magic = CSRStatus(16)
         self._reset = CSR()
@@ -68,7 +72,7 @@ def get_csrs(self):
         return [self._magic, self._reset, self._shoot] + self._dma.get_csrs()
 
 
-class MemtestReader(Module):
+class Reader(Module):
     def __init__(self, lasmim):
         self._magic = CSRStatus(16)
         self._reset = CSR()

diff --git a/misoc/cores/spi/__init__.py b/misoc/cores/spi/__init__.py
@@ -0,0 +1 @@
+from misoc.spi.core import SPIMaster
diff --git a/misoclib/com/spi/__init__.py → misoc/cores/spi/core.py b/misoclib/com/spi/__init__.py → misoc/cores/spi/core.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 from migen.genlib.fsm import FSM, NextState
 
@@ -17,7 +17,7 @@ def __init__(self, pads, width=24, div=2, cpha=1):
 
         self.irq = Signal()
 
-    ###
+        ###
 
         # ctrl
         start = Signal()
@@ -33,7 +33,6 @@ def __init__(self, pads, width=24, div=2, cpha=1):
 
         # clk
         i = Signal(max=div)
-        clk_en = Signal()
         set_clk = Signal()
         clr_clk = Signal()
         self.sync += [
@@ -124,7 +123,6 @@ def __init__(self, pads, width=24, div=2, cpha=1):
 
         # mosi
         if hasattr(pads, "mosi"):
-            mosi = Signal()
             sr_mosi = Signal(width)
 
             # (cpha = 1: propagated on clk rising edge)

diff --git a/misoclib/com/spi/test/spi_master_tb.py → misoc/cores/spi/test.py b/misoclib/com/spi/test/spi_master_tb.py → misoc/cores/spi/test.py
@@ -1,8 +1,8 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 from migen.sim.generic import run_simulation
 
-from misoclib.com.spi import SPIMaster
+from misoc.com.spi import SPIMaster
 
 
 class SPISlave(Module):

diff --git a/misoclib/mem/flash/spiflash.py → misoc/cores/spi_flash.py b/misoclib/mem/flash/spiflash.py → misoc/cores/spi_flash.py
@@ -1,9 +1,9 @@
-from migen.fhdl.std import *
-from migen.bus.transactions import *
-from migen.bus import wishbone
+from migen import *
 from migen.genlib.misc import timeline
-from migen.genlib.record import Record
-from migen.bank.description import AutoCSR, CSRStorage, CSRStatus
+
+from misoc.interconnect import wishbone
+from misoc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus
+
 
 _FAST_READ = 0x0b
 _DIOFR = 0xbb
@@ -35,7 +35,7 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True):
         Optionally supports software bitbanging (for write, erase, or other commands).
         """
         self.bus = bus = wishbone.Interface()
-        spi_width = flen(pads.dq)
+        spi_width = len(pads.dq)
         if with_bitbang:
             self.bitbang = CSRStorage(4)
             self.miso = CSRStatus()
@@ -46,7 +46,7 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True):
         cs_n = Signal(reset=1)
         clk = Signal()
         dq_oe = Signal()
-        wbone_width = flen(bus.dat_r)
+        wbone_width = len(bus.dat_r)
 
 
         read_cmd_params = {
@@ -142,40 +142,3 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True):
             t += dt
 
         self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq)
-
-
-class SpiFlashTB(Module):
-    def __init__(self):
-        self.submodules.master = wishbone.Initiator(self.gen_reads())
-        self.pads = Record([("cs_n", 1), ("clk", 1), ("dq", 4)])
-        self.submodules.slave = SpiFlash(self.pads)
-        self.submodules.tap = wishbone.Tap(self.slave.bus)
-        self.submodules.intercon = wishbone.InterconnectPointToPoint(
-                self.master.bus, self.slave.bus)
-        self.cycle = 0
-
-    def gen_reads(self):
-        for a in range(10):
-            t = TRead(a)
-            yield t
-            print("read {} in {} cycles(s)".format(t.data, t.latency))
-
-    def do_simulation(self, selfp):
-        if selfp.pads.cs_n:
-            self.cycle = 0
-        else:
-            self.cycle += 1
-            if not selfp.slave.dq.oe:
-                selfp.slave.dq.i = self.cycle & 0xf
-    do_simulation.passive = True
-
-if __name__ == "__main__":
-    from migen.sim.generic import run_simulation
-    from migen.fhdl import verilog
-
-    pads = Record([("cs_n", 1), ("clk", 1), ("dq", 4)])
-    s = SpiFlash(pads)
-    print(verilog.convert(s, ios={pads.clk, pads.cs_n, pads.dq, s.bus.adr,
-        s.bus.dat_r, s.bus.cyc, s.bus.ack, s.bus.stb}))
-
-    run_simulation(SpiFlashTB(), vcd_name="spiflash.vcd")
diff --git a/misoclib/cpu/timer.py → misoc/cores/timer.py b/misoclib/cpu/timer.py → misoc/cores/timer.py
@@ -1,6 +1,7 @@
-from migen.fhdl.std import *
-from migen.bank.description import *
-from migen.bank.eventmanager import *
+from migen import *
+
+from misoc.interconnect.csr import *
+from misoc.interconnect.csr_eventmanager import *
 
 
 class Timer(Module, AutoCSR):

diff --git a/misoc/cores/uart/__init__.py b/misoc/cores/uart/__init__.py
@@ -0,0 +1 @@
+from misoc.cores.uart.core import UART, RS232PHY
diff --git a/misoclib/com/uart/phy/serial.py → misoc/cores/uart/core.py b/misoclib/com/uart/phy/serial.py → misoc/cores/uart/core.py
@@ -1,13 +1,18 @@
-from migen.fhdl.std import *
+from migen import *
+from migen.genlib.record import Record
 from migen.genlib.cdc import MultiReg
-from migen.bank.description import *
-from migen.flow.actor import Sink, Source
 
+from misoc.interconnect.csr import *
+from misoc.interconnect.csr_eventmanager import *
+from misoc.interconnect.stream import Source, Sink, SyncFIFO, AsyncFIFO
 
-class UARTPHYSerialRX(Module):
+
+class RS232PHYRX(Module):
     def __init__(self, pads, tuning_word):
         self.source = Source([("data", 8)])
-        ###
+
+        # # #
+
         uart_clk_rxen = Signal()
         phase_accumulator_rx = Signal(32)
 
@@ -54,10 +59,12 @@ def __init__(self, pads, tuning_word):
                 )
 
 
-class UARTPHYSerialTX(Module):
+class RS232PHYTX(Module):
     def __init__(self, pads, tuning_word):
         self.sink = Sink([("data", 8)])
-        ###
+
+        # # #
+
         uart_clk_txen = Signal()
         phase_accumulator_tx = Signal(32)
 
@@ -96,9 +103,60 @@ def __init__(self, pads, tuning_word):
         ]
 
 
-class UARTPHYSerial(Module, AutoCSR):
+class RS232PHY(Module, AutoCSR):
     def __init__(self, pads, clk_freq, baudrate=115200):
         self._tuning_word = CSRStorage(32, reset=int((baudrate/clk_freq)*2**32))
-        self.submodules.tx = UARTPHYSerialTX(pads, self._tuning_word.storage)
-        self.submodules.rx = UARTPHYSerialRX(pads, self._tuning_word.storage)
+        self.submodules.tx = RS232PHYTX(pads, self._tuning_word.storage)
+        self.submodules.rx = RS232PHYRX(pads, self._tuning_word.storage)
         self.sink, self.source = self.tx.sink, self.rx.source
+
+
+def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
+    if sink_cd != source_cd:
+        fifo = AsyncFIFO([("data", 8)], depth)
+        return ClockDomainsRenamer({"write": sink_cd, "read": source_cd})(fifo)
+    else:
+        return SyncFIFO([("data", 8)], depth)
+
+
+class UART(Module, AutoCSR):
+    def __init__(self, phy,
+                 tx_fifo_depth=16,
+                 rx_fifo_depth=16,
+                 phy_cd="sys"):
+        self._rxtx = CSR(8)
+        self._txfull = CSRStatus()
+        self._rxempty = CSRStatus()
+
+        self.submodules.ev = EventManager()
+        self.ev.tx = EventSourceProcess()
+        self.ev.rx = EventSourceProcess()
+        self.ev.finalize()
+
+        # # #
+
+        # TX
+        tx_fifo = _get_uart_fifo(tx_fifo_depth, source_cd=phy_cd)
+        self.submodules += tx_fifo
+
+        self.comb += [
+            tx_fifo.sink.stb.eq(self._rxtx.re),
+            tx_fifo.sink.data.eq(self._rxtx.r),
+            self._txfull.status.eq(~tx_fifo.sink.ack),
+            Record.connect(tx_fifo.source, phy.sink),
+            # Generate TX IRQ when tx_fifo becomes non-full
+            self.ev.tx.trigger.eq(~tx_fifo.sink.ack)
+        ]
+
+        # RX
+        rx_fifo = _get_uart_fifo(rx_fifo_depth, sink_cd=phy_cd)
+        self.submodules += rx_fifo
+
+        self.comb += [
+            Record.connect(phy.source, rx_fifo.sink),
+            self._rxempty.status.eq(~rx_fifo.source.stb),
+            self._rxtx.w.eq(rx_fifo.source.data),
+            rx_fifo.source.ack.eq(self.ev.rx.clear),
+            # Generate RX IRQ when tx_fifo becomes non-empty
+            self.ev.rx.trigger.eq(~rx_fifo.source.stb)
+        ]
diff --git a/misoclib/com/uart/test/test_serial_phy.py → misoc/cores/uart/test.py b/misoclib/com/uart/test/test_serial_phy.py → misoc/cores/uart/test.py
diff --git a/misoc/integration/__init__.py b/misoc/integration/__init__.py
@@ -0,0 +1,2 @@
+from misoc.integration.soc_core import SoCCore
+from misoc.integration.soc_sdram import SoCSDRAM
diff --git a/misoc/integration/builder.py b/misoc/integration/builder.py
@@ -0,0 +1,168 @@
+import os
+import subprocess
+import struct
+
+from misoc.integration import cpu_interface, soc_sdram, sdram_init
+
+
+__all__ = ["misoc_software_packages", "misoc_directory",
+           "Builder", "builder_args", "builder_argdict"]
+
+
+# in build order (for dependencies)
+misoc_software_packages = [
+    "libbase",
+    "libcompiler_rt",
+    "libdyld",
+    "libnet",
+    "libunwind",
+    "bios"
+]
+
+
+misoc_directory = os.path.abspath(os.path.join(os.path.dirname(__file__), ".."))
+
+
+def _makefile_escape(s):
+    return s.replace("\\", "\\\\")
+
+
+class Builder:
+    def __init__(self, soc, output_dir=None,
+                 compile_software=True, compile_gateware=True,
+                 gateware_toolchain_path=None,
+                 csr_csv=None):
+        self.soc = soc
+        if output_dir is None:
+            output_dir = "misoc_{}_{}".format(
+                soc.__class__.__name__.lower(),
+                soc.platform.name)
+        # From Python doc: makedirs() will become confused if the path
+        # elements to create include '..'
+        self.output_dir = os.path.abspath(output_dir)
+        self.compile_software = compile_software
+        self.compile_gateware = compile_gateware
+        self.gateware_toolchain_path = gateware_toolchain_path
+        self.csr_csv = csr_csv
+
+        self.software_packages = []
+        for name in misoc_software_packages:
+            self.add_software_package(
+                name, os.path.join(misoc_directory, "software", name))
+
+    def add_software_package(self, name, src_dir):
+        self.software_packages.append((name, src_dir))
+
+    def _generate_includes(self):
+        cpu_type = self.soc.cpu_type
+        memory_regions = self.soc.get_memory_regions()
+        flash_boot_address = getattr(self.soc, "flash_boot_address", None)
+        csr_regions = self.soc.get_csr_regions()
+        constants = self.soc.get_constants()
+        if isinstance(self.soc, soc_sdram.SoCSDRAM) and self.soc._sdram_phy:
+            sdram_phy_settings = self.soc._sdram_phy[0].settings
+        else:
+            sdram_phy_settings = None
+
+        buildinc_dir = os.path.join(self.output_dir, "software", "include")
+        generated_dir = os.path.join(buildinc_dir, "generated")
+        os.makedirs(generated_dir, exist_ok=True)
+        with open(os.path.join(generated_dir, "variables.mak"), "w") as f:
+            def define(k, v):
+                f.write("{}={}\n".format(k, _makefile_escape(v)))
+            for k, v in cpu_interface.get_cpu_mak(cpu_type):
+                define(k, v)
+            define("MISOC_DIRECTORY", misoc_directory)
+            define("BUILDINC_DIRECTORY", buildinc_dir)
+            for name, src_dir in self.software_packages:
+                define(name.upper() + "_DIRECTORY", src_dir)
+
+        with open(os.path.join(generated_dir, "output_format.ld"), "w") as f:
+            f.write(cpu_interface.get_linker_output_format(cpu_type))
+        with open(os.path.join(generated_dir, "regions.ld"), "w") as f:
+            f.write(cpu_interface.get_linker_regions(memory_regions))
+
+        with open(os.path.join(generated_dir, "mem.h"), "w") as f:
+            f.write(cpu_interface.get_mem_header(memory_regions, flash_boot_address))
+        with open(os.path.join(generated_dir, "csr.h"), "w") as f:
+            f.write(cpu_interface.get_csr_header(csr_regions, constants))
+
+        if sdram_phy_settings is not None:
+            with open(os.path.join(generated_dir, "sdram_phy.h"), "w") as f:
+                f.write(sdram_init.get_sdram_phy_header(sdram_phy_settings))
+
+        if self.csr_csv is not None:
+            with open(self.csr_csv, "w") as f:
+                f.write(cpu_interface.get_csr_csv(csr_regions))
+
+    def _generate_software(self):
+        for name, src_dir in self.software_packages:
+            dst_dir = os.path.join(self.output_dir, "software", name)
+            os.makedirs(dst_dir, exist_ok=True)
+            src = os.path.join(src_dir, "Makefile")
+            dst = os.path.join(dst_dir, "Makefile")
+            try:
+                os.remove(dst)
+            except FileNotFoundError:
+                pass
+            os.symlink(src, dst)
+            if self.compile_software:
+                subprocess.check_call(["make", "-C", dst_dir])
+
+    def _initialize_rom(self):
+        bios_file = os.path.join(self.output_dir, "software", "bios",
+                                 "bios.bin")
+        if self.soc.integrated_rom_size:
+            with open(bios_file, "rb") as boot_file:
+                boot_data = []
+                while True:
+                    w = boot_file.read(4)
+                    if not w:
+                        break
+                    boot_data.append(struct.unpack(">I", w)[0])
+            self.soc.initialize_rom(boot_data)
+
+    def build(self):
+        self.soc.finalize()
+
+        if self.soc.integrated_rom_size and not self.compile_software:
+            raise ValueError("Software must be compiled in order to "
+                             "intitialize integrated ROM")
+
+        self._generate_includes()
+        self._generate_software()
+        self._initialize_rom()
+        if self.gateware_toolchain_path is None:
+            kwargs = dict()
+        else:
+            kwargs = {"toolchain_path": self.gateware_toolchain_path}
+        self.soc.build(build_dir=os.path.join(self.output_dir, "gateware"),
+                       run=self.compile_gateware, **kwargs)
+
+
+def builder_args(parser):
+    parser.add_argument("--output-dir", default=None,
+                        help="output directory for generated "
+                             "source files and binaries")
+    parser.add_argument("--no-compile-software", action="store_true",
+                        help="do not compile the software, only generate "
+                             "build infrastructure")
+    parser.add_argument("--no-compile-gateware", action="store_true",
+                        help="do not compile the gateware, only generate "
+                             "HDL source files and build scripts")
+    parser.add_argument("--gateware-toolchain-path", default=None,
+                        help="set gateware toolchain (ISE, Quartus, etc.) "
+                             "installation path")
+    parser.add_argument("--csr-csv", default=None,
+                        help="store CSR map in CSV format into the "
+                             "specified file")
+
+
+def builder_argdict(args):
+    return {
+        "output_dir": args.output_dir,
+        "compile_software": not args.no_compile_software,
+        "compile_gateware": not args.no_compile_gateware,
+        "gateware_toolchain_path": args.gateware_toolchain_path,
+        "csr_csv": args.csr_csv
+    }
diff --git a/misoclib/soc/cpuif.py → misoc/integration/cpu_interface.py b/misoclib/soc/cpuif.py → misoc/integration/cpu_interface.py
@@ -1,19 +1,25 @@
-from migen.fhdl.std import *
-from migen.bank.description import CSRStatus
+from migen import *
 
+from misoc.interconnect.csr import CSRStatus
 
-def get_cpu_mak(cpu_type):
-    if cpu_type == "lm32":
+
+def get_cpu_mak(cpu):
+    if cpu == "lm32":
         triple = "lm32-elf"
         cpuflags = "-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled"
         clang = ""
-    elif cpu_type == "or1k":
+    elif cpu == "or1k":
         triple = "or1k-linux"
         cpuflags = "-mhard-mul -mhard-div -mror -mffl1 -maddc"
         clang = "1"
     else:
-        raise ValueError("Unsupported CPU type: "+cpu_type)
-    return "TRIPLE={}\nCPU={}\nCPUFLAGS={}\nCLANG={}".format(triple, cpu_type, cpuflags, clang)
+        raise ValueError("Unsupported CPU type: "+cpu)
+    return [
+        ("TRIPLE", triple),
+        ("CPU", cpu),
+        ("CPUFLAGS", cpuflags),
+        ("CLANG", clang)
+    ]
 
 
 def get_linker_output_format(cpu_type):

diff --git a/misoclib/mem/sdram/phy/initsequence.py → misoc/integration/sdram_init.py b/misoclib/mem/sdram/phy/initsequence.py → misoc/integration/sdram_init.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import log2_int
+from migen import log2_int
 
 
 def get_sdram_phy_header(sdram_phy_settings):

diff --git a/misoclib/soc/__init__.py → misoc/integration/soc_core.py b/misoclib/soc/__init__.py → misoc/integration/soc_core.py
@@ -1,20 +1,19 @@
 from operator import itemgetter
 
-from migen.fhdl.std import *
-from migen.bank import csrgen
-from migen.bus import wishbone, csr, wishbone2csr
+from migen import *
 
-from misoclib.com.uart.phy import UARTPHY
-from misoclib.com import uart
-from misoclib.cpu import lm32, mor1kx
-from misoclib.cpu import identifier, timer
+from misoc.cores import lm32, mor1kx, identifier, timer, uart
+from misoc.interconnect import wishbone, csr_bus, wishbone2csr
+
+
+__all__ = ["mem_decoder", "SoCCore", "soc_core_args", "soc_core_argdict"]
 
 
 def mem_decoder(address, start=26, end=29):
     return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
 
 
-class SoC(Module):
+class SoCCore(Module):
     csr_map = {
         "crg":        0,  # user
         "uart_phy":   1,  # provided by default (optional)
@@ -40,7 +39,7 @@ def __init__(self, platform, clk_freq,
                 integrated_sram_size=4096,
                 integrated_main_ram_size=0,
                 shadow_base=0x80000000,
-                with_csr=True, csr_data_width=8, csr_address_width=14,
+                csr_data_width=8, csr_address_width=14,
                 with_uart=True, uart_baudrate=115200,
                 with_identifier=True,
                 with_timer=True):
@@ -63,7 +62,6 @@ def __init__(self, platform, clk_freq,
 
         self.shadow_base = shadow_base
 
-        self.with_csr = with_csr
         self.csr_data_width = csr_data_width
         self.csr_address_width = csr_address_width
 
@@ -74,52 +72,44 @@ def __init__(self, platform, clk_freq,
         self._wb_masters = []
         self._wb_slaves = []
 
-        if cpu_type != "none":
-            if cpu_type == "lm32":
-                self.add_cpu_or_bridge(lm32.LM32(platform, self.cpu_reset_address))
-            elif cpu_type == "or1k":
-                self.add_cpu_or_bridge(mor1kx.MOR1KX(platform, self.cpu_reset_address))
-            else:
-                raise ValueError("Unsupported CPU type: {}".format(cpu_type))
-            self.add_wb_master(self.cpu_or_bridge.ibus)
-            self.add_wb_master(self.cpu_or_bridge.dbus)
-
-            if integrated_rom_size:
-                self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True)
-                self.register_rom(self.rom.bus, integrated_rom_size)
-
-            if integrated_sram_size:
-                self.submodules.sram = wishbone.SRAM(integrated_sram_size)
-                self.register_mem("sram", self.mem_map["sram"], self.sram.bus, integrated_sram_size)
-
-            # Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
-            if integrated_main_ram_size:
-                self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size)
-                self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)
-
-        if with_csr:
-            self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(csr_data_width, csr_address_width))
-            self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
-
-            if with_uart:
-                self.submodules.uart_phy = UARTPHY(platform.request("serial"), clk_freq, uart_baudrate)
-                self.submodules.uart = uart.UART(self.uart_phy)
-
-            if with_identifier:
-                platform_id = 0x554E if not hasattr(platform, "identifier") else platform.identifier
-                self.submodules.identifier = identifier.Identifier(platform_id, int(clk_freq))
-
-            if with_timer:
-                self.submodules.timer0 = timer.Timer()
-
-    def add_cpu_or_bridge(self, cpu_or_bridge):
-        if self.finalized:
-            raise FinalizeError
-        if hasattr(self, "cpu_or_bridge"):
-            raise NotImplementedError("More than one CPU is not supported")
-        self.submodules.cpu_or_bridge = cpu_or_bridge
+        if cpu_type == "lm32":
+            self.submodules.cpu = lm32.LM32(platform, self.cpu_reset_address)
+        elif cpu_type == "or1k":
+            self.submodules.cpu = mor1kx.MOR1KX(platform, self.cpu_reset_address)
+        else:
+            raise ValueError("Unsupported CPU type: {}".format(cpu_type))
+        self.add_wb_master(self.cpu.ibus)
+        self.add_wb_master(self.cpu.dbus)
+
+        if integrated_rom_size:
+            self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True)
+            self.register_rom(self.rom.bus, integrated_rom_size)
+
+        if integrated_sram_size:
+            self.submodules.sram = wishbone.SRAM(integrated_sram_size)
+            self.register_mem("sram", self.mem_map["sram"], self.sram.bus, integrated_sram_size)
+
+        # Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
+        if integrated_main_ram_size:
+            self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size)
+            self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)
+
+        self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
+            bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
+        self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
+
+        if with_uart:
+            self.submodules.uart_phy = uart.RS232PHY(platform.request("serial"), clk_freq, uart_baudrate)
+            self.submodules.uart = uart.UART(self.uart_phy)
+
+        if with_identifier:
+            platform_id = 0x554E if not hasattr(platform, "identifier") else platform.identifier
+            self.submodules.identifier = identifier.Identifier(platform_id, int(clk_freq))
+
+        if with_timer:
+            self.submodules.timer0 = timer.Timer()
 
-    def init_rom(self, data):
+    def initialize_rom(self, data):
         self.rom.mem.init = data
 
     def add_wb_master(self, wbm):
@@ -177,28 +167,47 @@ def get_constants(self):
 
     def do_finalize(self):
         registered_mems = {regions[0] for regions in self._memory_regions}
-        if self.cpu_type != "none":
-            for mem in "rom", "sram":
-                if mem not in registered_mems:
-                    raise FinalizeError("CPU needs a {} to be registered with SoC.register_mem()".format(mem))
+        for mem in "rom", "sram":
+            if mem not in registered_mems:
+                raise FinalizeError("CPU needs a {} to be registered with register_mem()".format(mem))
 
         # Wishbone
         self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
             self._wb_slaves, register=True)
 
         # CSR
-        if self.with_csr:
-            self.submodules.csrbankarray = csrgen.BankArray(self,
-                lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
-                data_width=self.csr_data_width, address_width=self.csr_address_width)
-            self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
-            for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
-                self.add_csr_region(name, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, csrs)
-            for name, memory, mapaddr, mmap in self.csrbankarray.srams:
-                self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, memory)
+        self.submodules.csrbankarray = csr_bus.CSRBankArray(self,
+            lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
+            data_width=self.csr_data_width, address_width=self.csr_address_width)
+        self.submodules.csrcon = csr_bus.Interconnect(
+            self.wishbone2csr.csr, self.csrbankarray.get_buses())
+        for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
+            self.add_csr_region(name, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, csrs)
+        for name, memory, mapaddr, mmap in self.csrbankarray.srams:
+            self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, memory)
 
         # Interrupts
-        if hasattr(self.cpu_or_bridge, "interrupt"):
-            for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
-                if hasattr(self, k):
-                    self.comb += self.cpu_or_bridge.interrupt[v].eq(getattr(self, k).ev.irq)
+        for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
+            if hasattr(self, k):
+                self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
+
+    def build(self, *args, **kwargs):
+        self.platform.build(self, *args, **kwargs)
+
+
+def soc_core_args(parser):
+    parser.add_argument("--cpu-type", default=None,
+                        help="select CPU: lm32, or1k")
+    parser.add_argument("--integrated-rom-size", default=None, type=int,
+                        help="size/enable the integrated (BIOS) ROM")
+    parser.add_argument("--integrated-main-ram-size", default=None, type=int,
+                        help="size/enable the integrated main RAM")
+
+
+def soc_core_argdict(args):
+    r = dict()
+    for a in "cpu_type", "integrated_rom_size", "integrated_main_ram_size":
+        arg = getattr(args, a)
+        if arg is not None:
+            r[a] = arg
+    return r
diff --git a/misoc/integration/soc_sdram.py b/misoc/integration/soc_sdram.py
@@ -0,0 +1,121 @@
+from migen import *
+from migen.genlib.record import *
+
+from misoc.interconnect import wishbone, wishbone2lasmi, lasmi_bus
+from misoc.interconnect.csr import AutoCSR
+from misoc.cores import dfii, minicon, lasmicon
+from misoc.integration.soc_core import *
+
+
+__all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
+
+
+class ControllerInjector(Module, AutoCSR):
+    def __init__(self, phy, controller_type, geom_settings, timing_settings):
+        self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits,
+                phy.settings.dfi_databits, phy.settings.nphases)
+        self.comb += Record.connect(self.dfii.master, phy.dfi)
+
+        if controller_type == "lasmicon":
+            self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings,
+                                                                        geom_settings,
+                                                                        timing_settings)
+            self.comb += Record.connect(controller.dfi, self.dfii.slave)
+
+            self.submodules.crossbar = lasmi_bus.LASMIxbar([controller.lasmic],
+                                                           controller.nrowbits)
+        elif controller_type == "minicon":
+            self.submodules.controller = controller = minicon.Minicon(phy.settings,
+                                                                      geom_settings,
+                                                                      timing_settings)
+            self.comb += Record.connect(controller.dfi, self.dfii.slave)
+        else:
+            raise ValueError("Unsupported SDRAM controller type")
+
+
+class SoCSDRAM(SoCCore):
+    csr_map = {
+        "sdram":           8,
+        "l2_cache":        9
+    }
+    csr_map.update(SoCCore.csr_map)
+
+    def __init__(self, platform, clk_freq, l2_size=8192, **kwargs):
+        SoCCore.__init__(self, platform, clk_freq, **kwargs)
+        self.l2_size = l2_size
+
+        self._sdram_phy = []
+        self._wb_sdram_ifs = []
+        self._wb_sdram = wishbone.Interface()
+
+    def add_wb_sdram_if(self, interface):
+        if self.finalized:
+            raise FinalizeError
+        self._wb_sdram_ifs.append(interface)
+
+    def register_sdram(self, phy, sdram_controller_type, geom_settings, timing_settings):
+        assert not self._sdram_phy
+        self._sdram_phy.append(phy)  # encapsulate in list to prevent CSR scanning
+
+        self.submodules.sdram = ControllerInjector(
+            phy, sdram_controller_type, geom_settings, timing_settings)
+
+        dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2
+        sdram_width = phy.settings.dfi_databits//dfi_databits_divisor
+        main_ram_size = 2**(geom_settings.bankbits +
+                            geom_settings.rowbits +
+                            geom_settings.colbits)*sdram_width//8
+        # XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories.
+        main_ram_size = min(main_ram_size, 256*1024*1024)
+        if self.l2_size:
+            self.add_constant("L2_SIZE", self.l2_size)
+
+        # add a Wishbone interface to the DRAM
+        wb_sdram = wishbone.Interface()
+        self.add_wb_sdram_if(wb_sdram)
+        self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size)
+
+        if sdram_controller_type == "lasmicon":
+            if self.l2_size:
+                lasmim = self.sdram.crossbar.get_master()
+                l2_cache = wishbone.Cache(self.l2_size//4, self._wb_sdram, wishbone.Interface(lasmim.dw))
+                # XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
+                # Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
+                # Remove this workaround when fixed by Xilinx.
+                from migen.build.xilinx.vivado import XilinxVivadoToolchain
+                if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
+                    from migen.fhdl.simplify import FullMemoryWE
+                    self.submodules.l2_cache = FullMemoryWE()(l2_cache)
+                else:
+                    self.submodules.l2_cache = l2_cache
+                self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_cache.slave, lasmim)
+        elif sdram_controller_type == "minicon":
+            if self.l2_size:
+                l2_cache = wishbone.Cache(self.l2_size//4, self._wb_sdram, self.sdram.controller.bus)
+                # XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
+                # Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
+                # Remove this workaround when fixed by Xilinx.
+                from migen.build.xilinx.vivado import XilinxVivadoToolchain
+                if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
+                    from migen.fhdl.simplify import FullMemoryWE
+                    self.submodules.l2_cache = FullMemoryWE()(l2_cache)
+                else:
+                    self.submodules.l2_cache = l2_cache
+            else:
+                self.submodules.converter = wishbone.Converter(self._wb_sdram, self.sdram.controller.bus)
+        else:
+            raise ValueError
+
+    def do_finalize(self):
+        if not self.integrated_main_ram_size:
+            if not self._sdram_phy:
+                raise FinalizeError("Need to call SDRAMSoC.register_sdram()")
+
+            # arbitrate wishbone interfaces to the DRAM
+            self.submodules.wb_sdram_con = wishbone.Arbiter(self._wb_sdram_ifs,
+                                                            self._wb_sdram)
+        SoCCore.do_finalize(self)
+
+
+soc_sdram_args = soc_core_args
+soc_sdram_argdict = soc_core_argdict
diff --git a/misoclib/mem/sdram/frontend/__init__.py → misoc/interconnect/__init__.py b/misoclib/mem/sdram/frontend/__init__.py → misoc/interconnect/__init__.py
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		from misoc.cores.dvi_sampler.core import DVISampler
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		from misoc.cores.framebuffer.core import Framebuffer
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		from misoc.cores.lasmicon.core import ControllerSettings, LASMIcon
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		from misoc.cores.uart.core import UART, RS232PHY
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1,2 @@
		from misoc.integration.soc_core import SoCCore
		from misoc.integration.soc_sdram import SoCSDRAM