m-labs · Nov 3, 2015 · Nov 3, 2015 · Nov 4, 2015 · Nov 4, 2015 · Nov 4, 2015
diff --git a/.gitignore b/.gitignore
@@ -5,7 +5,6 @@ __pycache__
 *.bin
 *.elf
 *.fbi
-soc/runtime/service_table.h
 doc/manual/_build
 /build
 /dist

diff --git a/.gitmodules b/.gitmodules
@@ -1,4 +1,4 @@
-[submodule "soc/runtime/lwip"]
-	path = soc/runtime/lwip
+[submodule "artiq/runtime/lwip"]
+	path = artiq/runtime/lwip
 	url = git://git.savannah.nongnu.org/lwip.git
     ignore = untracked
diff --git a/.travis.yml b/.travis.yml
@@ -15,7 +15,6 @@ install:
   - if [ $TRAVIS_PULL_REQUEST != false ]; then BUILD_SOC=none; fi
   - if [ $BUILD_SOC != none ]; then ./.travis/get-xilinx.sh; fi
   - if [ $BUILD_SOC != none ]; then ./.travis/get-toolchain.sh; fi
-  - if [ $BUILD_SOC != none ]; then ./.travis/get-misoc.sh; fi
   - . ./.travis/get-anaconda.sh
   - source $HOME/miniconda/bin/activate py35
   - conda install -q pip coverage anaconda-client cython

diff --git a/.travis/get-misoc.sh b/.travis/get-misoc.sh
diff --git a/.travis/get-xilinx.sh b/.travis/get-xilinx.sh
@@ -26,13 +26,13 @@ echo "$secret" | gpg --passphrase-fd 0 Xilinx.lic.gpg
 mkdir -p ~/.Xilinx
 mv Xilinx.lic ~/.Xilinx/Xilinx.lic
 
-git clone https://github.com/fallen/impersonate_macaddress
+git clone https://github.com/m-labs/impersonate_macaddress
 make -C impersonate_macaddress
 # Tell mibuild where Xilinx toolchains are installed
 # and feed it the mac address corresponding to the license
 cat >> $HOME/.m-labs/build_settings.sh << EOF
-MISOC_EXTRA_VIVADO_CMDLINE="-Ob vivado_path $HOME/Xilinx/Vivado"
-MISOC_EXTRA_ISE_CMDLINE="-Ob ise_path $HOME/opt/Xilinx/"
+MISOC_EXTRA_ISE_CMDLINE="--gateware-toolchain-path $HOME/opt/Xilinx/"
+MISOC_EXTRA_VIVADO_CMDLINE="--gateware-toolchain-path $HOME/Xilinx/Vivado"
 export MACADDR=$macaddress
 export LD_PRELOAD=$PWD/impersonate_macaddress/impersonate_macaddress.so
 EOF
diff --git a/artiq/frontend/artiq_flash.sh b/artiq/frontend/artiq_flash.sh
@@ -11,17 +11,14 @@ def run(script):
 		file.close()
 
 run("""
-# exit on error
 set -e
-# print commands
-#set -x
 
 ARTIQ_PREFIX=$(python3 -c "import artiq; print(artiq.__path__[0])")
 
 # Default is kc705
 BOARD=kc705
-# Default mezzanine board is nist_qc1
-MEZZANINE_BOARD=nist_qc1
+# Default hardware adapter is qc1
+HARDWARE_ADAPTER=qc1
 
 while getopts "bBrht:d:f:m:" opt
 do
@@ -67,14 +64,14 @@ do
 			fi
 			;;
 		m)
-			if [ "$OPTARG" == "nist_qc1" ]
+			if [ "$OPTARG" == "qc1" ]
 			then
-				MEZZANINE_BOARD=nist_qc1
-			elif [ "$OPTARG" == "nist_qc2" ]
+				HARDWARE_ADAPTER=qc1
+			elif [ "$OPTARG" == "qc2" ]
 			then
-				MEZZANINE_BOARD=nist_qc2
+				HARDWARE_ADAPTER=qc2
 			else
-				echo "KC705 mezzanine board is either nist_qc1 or nist_qc2"
+				echo "Hardware adapter should be qc1 or qc2"
 				exit 1
 			fi
 			;;
@@ -88,8 +85,8 @@ do
 			echo "-B  Flash BIOS"
 			echo "-r  Flash ARTIQ runtime"
 			echo "-h  Show this help message"
-			echo "-t  Target (kc705, pipistrello, default is: kc705)"
-			echo "-m  Mezzanine board (nist_qc1, nist_qc2, default is: nist_qc1)"
+			echo "-t  Target (kc705/pipistrello, default: kc705)"
+			echo "-m  Hardware adapter (qc1/qc2, default: qc1)"
 			echo "-f  Flash storage image generated with artiq_mkfs"
 			echo "-d  Directory containing the binaries to be flashed"
 			exit 1
@@ -129,30 +126,28 @@ fi
 if [ "$BOARD" == "kc705" ]
 then
 	UDEV_RULES=99-kc705.rules
-	BITSTREAM=artiq_kc705-${MEZZANINE_BOARD}-kc705.bit
 	CABLE=jtaghs1_fast
 	PROXY=bscan_spi_kc705.bit
 	BIOS_ADDR=0xaf0000
 	RUNTIME_ADDR=0xb00000
-	RUNTIME_FILE=runtime.fbi
 	FS_ADDR=0xb40000
 	if [ -z "$BIN_PREFIX" ]
 	then
-		RUNTIME_FILE=${MEZZANINE_BOARD}/runtime.fbi
-		BIN_PREFIX=$ARTIQ_PREFIX/binaries/kc705
+		BIN_PREFIX=$ARTIQ_PREFIX/binaries/kc705-$HARDWARE_ADAPTER
 	fi
 	search_for_proxy $PROXY
 elif [ "$BOARD" == "pipistrello" ]
 then
 	UDEV_RULES=99-papilio.rules
-	BITSTREAM=artiq_pipistrello-nist_qc1-pipistrello.bit
 	CABLE=papilio
 	PROXY=bscan_spi_lx45_csg324.bit
 	BIOS_ADDR=0x170000
 	RUNTIME_ADDR=0x180000
-	RUNTIME_FILE=runtime.fbi
 	FS_ADDR=0x1c0000
-	if [ -z "$BIN_PREFIX" ]; then BIN_PREFIX=$ARTIQ_PREFIX/binaries/pipistrello; fi
+	if [ -z "$BIN_PREFIX" ];
+	then
+		BIN_PREFIX=$ARTIQ_PREFIX/binaries/pipistrello-$HARDWARE_ADAPTER
+	fi
 	search_for_proxy $PROXY
 fi
 
@@ -195,7 +190,7 @@ fi
 if [ "${FLASH_BITSTREAM}" == "1" ]
 then
 	echo "Flashing FPGA bitstream..."
-	xc3sprog -v -c $CABLE -I$PROXY_PATH/$PROXY $BIN_PREFIX/$BITSTREAM:w:0x0:BIT
+	xc3sprog -v -c $CABLE -I$PROXY_PATH/$PROXY $BIN_PREFIX/top.bit:w:0x0:BIT
 fi
 
 if [ "${FLASH_BIOS}" == "1" ]
@@ -207,7 +202,7 @@ fi
 if [ "${FLASH_RUNTIME}" == "1" ]
 then
 	echo "Flashing ARTIQ runtime..."
-	xc3sprog -v -c $CABLE -I$PROXY_PATH/$PROXY $BIN_PREFIX/${RUNTIME_FILE}:w:$RUNTIME_ADDR:BIN
+	xc3sprog -v -c $CABLE -I$PROXY_PATH/$PROXY $BIN_PREFIX/runtime.fbi:w:$RUNTIME_ADDR:BIN
 fi
 echo "Done."
 xc3sprog -v -c $CABLE -R > /dev/null 2>&1

diff --git a/artiq/frontend/artiq_gui.py b/artiq/frontend/artiq_gui.py
@@ -10,7 +10,7 @@
 from quamash import QEventLoop, QtGui, QtCore
 from pyqtgraph import dockarea
 
-from artiq.tools import verbosity_args, init_logger
+from artiq.tools import verbosity_args, init_logger, artiq_dir
 from artiq.protocols.pc_rpc import AsyncioClient
 from artiq.gui.state import StateManager
 from artiq.gui.explorer import ExplorerDock
@@ -21,10 +21,6 @@
 from artiq.gui.console import ConsoleDock
 
 
-data_dir = os.path.join(os.path.abspath(os.path.dirname(__file__)),
-                        "..", "gui")
-
-
 def get_argparser():
     parser = argparse.ArgumentParser(description="ARTIQ GUI client")
     parser.add_argument(
@@ -46,7 +42,8 @@ def get_argparser():
 class MainWindow(QtGui.QMainWindow):
     def __init__(self, app, server):
         QtGui.QMainWindow.__init__(self)
-        self.setWindowIcon(QtGui.QIcon(os.path.join(data_dir, "icon.png")))
+        icon = QtGui.QIcon(os.path.join(artiq_dir, "gui", "icon.png"))
+        self.setWindowIcon(icon)
         self.setWindowTitle("ARTIQ - {}".format(server))
         self.exit_request = asyncio.Event()
 

diff --git a/artiq/frontend/thorlabs_tcube_controller.py b/artiq/frontend/thorlabs_tcube_controller.py
@@ -11,8 +11,8 @@
 def get_argparser():
     parser = argparse.ArgumentParser()
     parser.add_argument("-P", "--product", required=True,
-                        help="type of the Thorlabs T-Cube device to control",
-                        choices=["tdc001", "tpz001"])
+                        help="type of the Thorlabs T-Cube device to control: "
+                             "tdc001/tpz001")
     parser.add_argument("-d", "--device", default=None,
                         help="serial device. See documentation for how to "
                              "specify a USB Serial Number.")
@@ -39,11 +39,19 @@ def main():
             dev = TdcSim()
         elif product == "tpz001":
             dev = TpzSim()
+        else:
+            print("Invalid product string (-P/--product), "
+                  "choose from tdc001 or tpz001")
+            sys.exit(1)
     else:
         if product == "tdc001":
             dev = Tdc(args.device)
         elif product == "tpz001":
             dev = Tpz(args.device)
+        else:
+            print("Invalid product string (-P/--product), "
+                  "choose from tdc001 or tpz001")
+            sys.exit(1)
 
     try:
         simple_server_loop({product: dev}, args.bind, args.port)

diff --git a/artiq/gateware/ad9xxx.py b/artiq/gateware/ad9xxx.py
@@ -1,18 +1,16 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fsm import *
 from migen.genlib.misc import WaitTimer
-from migen.bus import wishbone
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
+from misoc.interconnect import wishbone
 
 
 class AD9xxx(Module):
     """Wishbone interface to the AD9858 and AD9914 DDS chips.
 
-    Addresses 0-2**flen(pads.a)-1 map the AD9xxx registers.
+    Addresses 0-2**len(pads.a)-1 map the AD9xxx registers.
 
-    Write to address 2**flen(pads.a) to pulse the FUD signal.
-    Address 2**flen(pads.a)+1 is a GPIO register that controls the
+    Write to address 2**len(pads.a) to pulse the FUD signal.
+    Address 2**len(pads.a)+1 is a GPIO register that controls the
     sel and reset signals. rst is mapped to bit 0, followed by sel.
 
     Write timing:
@@ -38,15 +36,15 @@ def __init__(self, pads,
                  read_wait_cycles=10, hiz_wait_cycles=3,
                  bus=None):
         if bus is None:
-            bus = wishbone.Interface(data_width=flen(pads.d))
+            bus = wishbone.Interface(data_width=len(pads.d))
         self.bus = bus
 
         # # #
 
-        dts = TSTriple(flen(pads.d))
+        dts = TSTriple(len(pads.d))
         self.specials += dts.get_tristate(pads.d)
         hold_address = Signal()
-        dr = Signal(flen(pads.d))
+        dr = Signal(len(pads.d))
         rx = Signal()
         self.sync += [
             If(~hold_address, pads.a.eq(bus.adr)),
@@ -56,9 +54,9 @@ def __init__(self, pads,
         ]
 
         if hasattr(pads, "sel"):
-            sel_len = flen(pads.sel)
+            sel_len = len(pads.sel)
         else:
-            sel_len = flen(pads.sel_n)
+            sel_len = len(pads.sel_n)
         gpio = Signal(sel_len + 1)
         gpio_load = Signal()
         self.sync += If(gpio_load, gpio.eq(bus.dat_w))
@@ -98,7 +96,7 @@ def __init__(self, pads,
 
         fsm.act("IDLE",
             If(bus.cyc & bus.stb,
-                If(bus.adr[flen(pads.a)],
+                If(bus.adr[len(pads.a)],
                     If(bus.adr[0],
                         NextState("GPIO")
                     ).Else(
@@ -157,20 +155,20 @@ def __init__(self, pads,
         )
 
 
-def _test_gen():
+def _test_gen(bus):
     # Test external bus writes
-    yield TWrite(4, 2)
-    yield TWrite(5, 3)
+    yield from bus.write(4, 2)
+    yield from bus.write(5, 3)
     yield
     # Test external bus reads
-    yield TRead(14)
-    yield TRead(15)
+    yield from bus.read(14)
+    yield from bus.read(15)
     yield
     # Test FUD
-    yield TWrite(64, 0)
+    yield from bus.write(64, 0)
     yield
     # Test GPIO
-    yield TWrite(65, 0xff)
+    yield from bus.write(65, 0xff)
     yield
 
 
@@ -185,14 +183,7 @@ def __init__(self):
         self.rst_n = Signal()
 
 
-class _TB(Module):
-    def __init__(self):
-        pads = _TestPads()
-        self.submodules.dut = AD9xxx(pads, drive_fud=True)
-        self.submodules.initiator = wishbone.Initiator(_test_gen())
-        self.submodules.interconnect = wishbone.InterconnectPointToPoint(
-            self.initiator.bus, self.dut.bus)
-
-
 if __name__ == "__main__":
-    run_simulation(_TB(), vcd_name="ad9xxx.vcd")
+    pads = _TestPads()
+    dut = AD9xxx(pads)
+    run_simulation(dut, _test_gen(dut.bus), vcd_name="ad9xxx.vcd")
diff --git a/artiq/gateware/amp/kernel_cpu.py b/artiq/gateware/amp/kernel_cpu.py
@@ -1,9 +1,8 @@
-from migen.fhdl.std import *
-from migen.bank.description import *
-from migen.bus import wishbone
-
-from misoclib.cpu import mor1kx
-from misoclib.soc import mem_decoder
+from migen import *
+from misoc.interconnect.csr import *
+from misoc.interconnect import wishbone
+from misoc.cores import mor1kx
+from misoc.integration.soc_core import mem_decoder
 
 
 class KernelCPU(Module):
@@ -23,9 +22,8 @@ def __init__(self, platform,
             self.cd_sys_kernel.clk.eq(ClockSignal()),
             self.cd_sys_kernel.rst.eq(self._reset.storage)
         ]
-        self.submodules.cpu = RenameClockDomains(
-            mor1kx.MOR1KX(platform, exec_address),
-            "sys_kernel")
+        self.submodules.cpu = ClockDomainsRenamer("sys_kernel")(
+            mor1kx.MOR1KX(platform, exec_address))
 
         # DRAM access
         self.wb_sdram = wishbone.Interface()

diff --git a/artiq/gateware/amp/mailbox.py b/artiq/gateware/amp/mailbox.py
@@ -1,5 +1,5 @@
-from migen.fhdl.std import *
-from migen.bus import wishbone
+from migen import *
+from misoc.interconnect import wishbone
 
 
 class Mailbox(Module):

diff --git a/artiq/gateware/nist_qc1.py b/artiq/gateware/nist_qc1.py
@@ -1,4 +1,4 @@
-from mibuild.generic_platform import *
+from migen.build.generic_platform import *
 
 
 papilio_adapter_io = [

diff --git a/artiq/gateware/nist_qc2.py b/artiq/gateware/nist_qc2.py
@@ -1,4 +1,4 @@
-from mibuild.generic_platform import *
+from migen.build.generic_platform import *
 
 
 fmc_adapter_io = [
-Original file line number
+Diff line change
@@ @@ -5,7 +5,6 @@ __pycache__ @@
     *.bin
     *.elf
     *.fbi
-    soc/runtime/service_table.h
     doc/manual/_build
     /build
     /dist