Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/misoc
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 989d8a7c2927
Choose a base ref
...
head repository: m-labs/misoc
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 1e47cfce2bca
Choose a head ref
  • 2 commits
  • 6 files changed
  • 1 contributor

Commits on May 26, 2015

  1. litesata: doc fixes

    sbourdeauducq committed May 26, 2015
    Copy the full SHA
    a9da892 View commit details
  2. Merge branch 'master' of https://github.com/m-labs/misoc

    Conflicts:
    	misoclib/mem/litesata/doc/source/docs/frontend/index.rst
    sbourdeauducq committed May 26, 2015
    Copy the full SHA
    1e47cfc View commit details
52 changes: 26 additions & 26 deletions misoclib/mem/litesata/doc/source/docs/frontend/index.rst
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
.. _frontend-index:

========================
===================
Frontend interfaces
========================
===================

All frontend modules of LiteSATA share the same user interface based on packets.
An interface has 2 endpoints:
@@ -12,8 +12,8 @@ An interface has 2 endpoints:

Packets and user commands/responses are described in the next sections.

Packets description
===================
Packet description
==================

Sink and Source endpoints use packets with additional parameters. A packet has the following signals:

@@ -39,16 +39,16 @@ User Commands

All transfers are initiated using the Sink endpoint of the interface which has the following signals:

- :code:`write`: 1 bit signal, indicates a write command.
- :code:`read`: 1 bit signal, indicaties a aread command.
- :code:`identify`: 1 bit signal, indicates an identify command. (used to get HDD informations).
- :code:`sector`: 48 bits signal, sector number for the write or read.
- :code:`count`: 16 bits signal, number of sectors for the write or read.
- :code:`data`: n x 32 bits signal, write data. (n depends of the frontend module)
- :code:`write`: 1 bit signal, indicates if we want to write data to the HDD.
- :code:`read`: 1 bit signal, indicates if we want to read data from the HDD.
- :code:`identify`: 1 bit signal, indicates if the command is an identify device command (use to get HDD information).
- :code:`sector`: 48 bits signal, the sector number we are going to write or read.
- :code:`count`: 16 bits signal, the number of sectors we are going to write or read.
- :code:`data`: n x 32 bits signal, the write data. (n depends of the frontend module)

.. tip::

- :code:`write`, :code:`read`, :code:`identify`, :code:`sector`, :code:`count` are parameters so remain constant for a packet duration.
- :code:`write`, :code:`read`, :code:`identify`, :code:`sector`, :code:`count` are parameters which must remain constant for the duration of the packet.
- :code:`sector`, :code:`count` are ignored during an :code:`identify` command.
- :code:`data` is ignored during a :code:`read` or :code:`identify` command.

@@ -57,22 +57,22 @@ User Responses

Responses are obtained from the Source endpoint which has the following signals:

- :code:`write`: 1 bit signal, indicates a write response.
- :code:`read`: 1 bit signal, indicaties a read response.
- :code:`identify`: 1 bit signal, indicates an identify response.
- :code:`last`: 1 bit signal, indicates it's the last packet of the response. (A response can be return in several packets)
- :code:`failed`: 1 bit signal, indicates that an error was detected in the response (CRC, FIS...)
- :code:`data`: n x 32 bits signal, read data. (n depends of the frontend module)
- :code:`write`: 1 bit signal, indicates if the command was a write.
- :code:`read`: 1 bit signal, indicates if the command was a read.
- :code:`identify`: 1 bit signal, indicates if the command was an identify device command.
- :code:`last`: 1 bit signal, indicates if this is the last packet of the response. (A response can be return in several packets)
- :code:`failed`: 1 bit signal, indicates if an error was detected in the response (CRC, FIS...)
- :code:`data`: n x 32 bits signal, the read data. (n depends of the frontend module)

.. tip::

- :code:`write`, :code:`read`, :code:`identify`, :code:`last` are parameters so remain constant for a packet duration.
- :code:`write`, :code:`read`, :code:`identify`, :code:`last` are parameters that must remain constant for the duration of a packet.
- :code:`data` can be ignored in the case of a :code:`write` or :code:`identify` command.
- in case of a :code:`read` command, read data packets are presented followed by an empty packet indicating the end of the transaction (last=1).

========================
================
Frontend modules
========================
================

LiteSATA provides a configurable and flexible frontend that can be used to:

@@ -82,7 +82,7 @@ LiteSATA provides a configurable and flexible frontend that can be used to:
Crossbar
========

The crossbar allows the user to request any number of ports for its application. It automatically arbitrates requests and dispatches responses to the corresponding ports.
The crossbar allows the user to request any number of ports for their application. It automatically arbitrates requests and dispatches responses to the corresponding ports.

The following example creates a crossbar and 2 user ports:

@@ -95,7 +95,7 @@ The following example creates a crossbar and 2 user ports:
Striping
========

The striping module segments data so that data is stored on N different controllers. (RAID0 equivalent)
The striping module segments data so that data is stored on N different controllers (RAID0 equivalent).

.. code-block:: python
@@ -120,7 +120,7 @@ The following example creates a striping with 2 HDDs:
Mirroring
=========

The mirroring module handles N controllers and provides N ports. (RAID1 equivalent)
The mirroring module handles N controllers and provides N ports (RAID1 equivalent).

Each port has its dedicated controller for reads:

@@ -146,7 +146,7 @@ Characteristics:
- total writes throughput = (slowest) :code:`controller`'s throughput
- total reads throughput = N x :code:`controller`'s throughput

It can be used for data redundancy and/or to increase total reads speed.
It can be used for data redundancy and/or to increase the total read speed.

The following example creates a mirroring with 2 HDDs:

@@ -156,8 +156,8 @@ The following example creates a mirroring with 2 HDDs:
:code:`sata_striping`'s :code:`ports[0]` and :code:`ports[1]` are the user interfaces.

Modules combinations
====================
Module combinations
===================

Since all frontend modules share the same interface, it's easy to combine them together.

Original file line number Diff line number Diff line change
@@ -7,5 +7,4 @@ Bug Reporting
- send us bug reports when something goes wrong
- send us the modifications and improvements you have done to LiteSATA.
The use of "git format-patch" is recommended. If your submission is large and
complex and/or you are not sure how to proceed, feel free to discuss with us
about it.
complex and/or you are not sure how to proceed, feel free to discuss it with us.
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
.. _sdk-download-and-install:

====================
Download and install
====================
Please follow Getting started section of LiteSATA README_.
=========================
Download and installation
=========================
Please follow the "Getting started" section of the LiteSATA README_.

.. _README: https://github.com/m-labs/misoc/blob/master/misoclib/mem/litesata/README
Original file line number Diff line number Diff line change
@@ -4,14 +4,13 @@
Getting Started
===============

Now you know why LiteSATA is :ref:`core for you <about>`, it's time to *get started*.
Now that you know why LiteSATA is the :ref:`core for you <about>`, it's time to *get started*.

This section provides a walk-through of :ref:`downloading and installing the tools`.
This section explains the procedure for :ref:`downloading and installing the tools`.

.. toctree::
:maxdepth: 1

downloads
FAQ
bug_reports

36 changes: 0 additions & 36 deletions misoclib/mem/litesata/doc/source/docs/index.rst

This file was deleted.

17 changes: 8 additions & 9 deletions misoclib/mem/litesata/doc/source/docs/intro/about.rst
Original file line number Diff line number Diff line change
@@ -1,18 +1,17 @@
.. _about:

================
==============
About LiteSATA
================
==============

LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
LiteSATA provides a small footprint and configurable SATA gen1/2 core.

LiteSATA is part of MiSoC libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of
components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
LiteSATA is part of the MiSoC libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in modern SoCs such as Ethernet, SATA, PCIe, SDRAM controller...

The core uses simple and specific streaming buses and will provides in the future
The core uses simple and specific streaming buses and will provide in the future
adapters to use standardized AXI or Avalon-ST streaming buses.

Since Python is used to describe the HDL, the core is highly and easily
Since Python is used to describe the gateware, the core is highly and easily
configurable.

The synthetizable BIST can be used as a starting point to integrate SATA in
@@ -22,8 +21,8 @@ LiteSATA uses technologies developed in partnership with M-Labs Ltd:
- Migen enables generating HDL with Python in an efficient way.
- MiSoC provides the basic blocks to build a powerful and small footprint SoC.

LiteSATA can be used as MiSoC library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core.
LiteSATA can be used as a Python library or can be integrated with your standard
design flow by generating the Verilog RTL that you will use as a standard core.

.. _about-toolchain: