m-labs · Jun 2, 2015 · Jun 2, 2015
Showing with 16 additions and 16 deletions.

+6 −4 misoclib/mem/sdram/core/minicon/__init__.py

+8 −3 misoclib/mem/sdram/phy/simphy.py

+2 −9 misoclib/soc/sdram.py
diff --git a/misoclib/mem/sdram/core/minicon/__init__.py b/misoclib/mem/sdram/core/minicon/__init__.py
@@ -1,7 +1,7 @@
 from migen.fhdl.std import *
 from migen.bus import wishbone
 from migen.genlib.fsm import FSM, NextState
-from migen.genlib.misc import optree, Counter, WaitTimer
+from migen.genlib.misc import optree, WaitTimer
 
 from misoclib.mem.sdram.phy import dfi as dfibus
 
@@ -61,12 +61,14 @@ class MiniconSettings:
     def __init__(self):
         pass
 
+
 class Minicon(Module):
     def __init__(self, phy_settings, geom_settings, timing_settings):
         if phy_settings.memtype in ["SDR"]:
             burst_length = phy_settings.nphases*1  # command multiplication*SDR
         elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
             burst_length = phy_settings.nphases*2  # command multiplication*DDR
+        burst_width = phy_settings.dfi_databits*phy_settings.nphases
         address_align = log2_int(burst_length)
 
         # # #
@@ -76,7 +78,7 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
             phy_settings.dfi_databits,
             phy_settings.nphases)
 
-        self.bus = bus = wishbone.Interface()
+        self.bus = bus = wishbone.Interface(burst_width)
 
         rdphase = phy_settings.rdphase
         wrphase = phy_settings.wrphase
@@ -203,11 +205,11 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
             dfi.phases[rdphase].we_n.eq(1),
             NextState("POST-REFRESH")
         )
+        fsm.delayed_enter("WRITE-LATENCY", "WRITE-ACK", phy_settings.write_latency-1)
         fsm.delayed_enter("TRP", "ACTIVATE", timing_settings.tRP-1)
-        fsm.delayed_enter("PRE-REFRESH", "REFRESH", timing_settings.tRP-1)
         fsm.delayed_enter("TRCD", "IDLE", timing_settings.tRCD-1)
+        fsm.delayed_enter("PRE-REFRESH", "REFRESH", timing_settings.tRP-1)
         fsm.delayed_enter("POST-REFRESH", "IDLE", timing_settings.tRFC-1)
-        fsm.delayed_enter("WRITE-LATENCY", "WRITE-ACK", phy_settings.write_latency-1)
 
         # DFI commands
         for phase in dfi.phases:

diff --git a/misoclib/mem/sdram/phy/simphy.py b/misoclib/mem/sdram/phy/simphy.py
@@ -13,7 +13,7 @@
 
 
 class Bank(Module):
-    def __init__(self, data_width, nrows, ncols):
+    def __init__(self, data_width, nrows, ncols, burst_length):
         self.activate = Signal()
         self.activate_row = Signal(max=nrows)
         self.precharge = Signal()
@@ -39,7 +39,7 @@ def __init__(self, data_width, nrows, ncols):
                 row.eq(self.activate_row)
             )
 
-        self.specials.mem = mem = Memory(data_width, nrows*ncols)
+        self.specials.mem = mem = Memory(data_width, nrows*ncols//burst_length)
         self.specials.write_port = write_port = mem.get_port(write_capable=True,
                                                              we_granularity=8)
         self.specials.read_port = read_port = mem.get_port(async_read=True)
@@ -89,6 +89,11 @@ def __init__(self, dfi, n):
 
 class SDRAMPHYSim(Module):
     def __init__(self, module, settings):
+        if settings.memtype in ["SDR"]:
+            burst_length = settings.nphases*1  # command multiplication*SDR
+        elif settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
+            burst_length = settings.nphases*2  # command multiplication*DDR
+
         addressbits = module.geom_settings.addressbits
         bankbits = module.geom_settings.bankbits
         rowbits = module.geom_settings.rowbits
@@ -110,7 +115,7 @@ def __init__(self, module, settings):
         self.submodules += phases
 
         # banks
-        banks = [Bank(data_width, nrows, ncols) for i in range(nbanks)]
+        banks = [Bank(data_width, nrows, ncols, burst_length) for i in range(nbanks)]
         self.submodules += banks
 
         # connect DFI phases to banks (cmds, write datapath)

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
@@ -70,15 +70,8 @@ def register_sdram_phy(self, phy):
 
         # MINICON frontend
         elif isinstance(self.sdram_controller_settings, MiniconSettings):
-            burst_width = phy.settings.dfi_databits*phy.settings.nphases
-            if burst_width == 32:
-                self.register_mem("main_ram", self.mem_map["main_ram"], self.sdram.controller.bus, main_ram_size)
-            elif burst_width < 32:
-                self.submodules.downconverter = downconverter = wishbone.DownConverter(32, burst_width)
-                self.comb += Record.connect(downconverter.wishbone_o, self.sdram.controller.bus)
-                self.register_mem("main_ram", self.mem_map["main_ram"], downconverter.wishbone_i, main_ram_size)
-            else:
-                raise NotImplementedError("Unsupported burst width of {} > 32".format(burst_width))
+            self.submodules.converter = wishbone.Converter(wishbone.Interface(), self.sdram.controller.bus)
+            self.register_mem("main_ram", self.mem_map["main_ram"], self.converter.master, main_ram_size)
 
     def do_finalize(self):
         if not self.integrated_main_ram_size: