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base repository: m-labs/migen
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compare: bd232f3f61b2
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  • 5 commits
  • 2 files changed
  • 1 contributor

Commits on Aug 18, 2014

  1. vivado: make tcl a list of commands, add reporting

    @jordens @sbourdeauducq
    jordens authored and sbourdeauducq committed Aug 18, 2014
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    7e77254 View commit details

  2. Signal.like: pass kwargs

    @jordens @sbourdeauducq
    jordens authored and sbourdeauducq committed Aug 18, 2014
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    b3d6991 View commit details

  3. Signal.__getitem__: raise TypeError and IndexError when appropriate

    @jordens @sbourdeauducq
    jordens authored and sbourdeauducq committed Aug 18, 2014
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    6036fff View commit details

  4. fhdl.structure: remove unused imports

    @jordens @sbourdeauducq
    jordens authored and sbourdeauducq committed Aug 18, 2014
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    ac2e961 View commit details

  5. fhdl.structure: do not permit clock domain names that start with numbers

    @jordens @sbourdeauducq
    jordens authored and sbourdeauducq committed Aug 18, 2014

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    bd232f3 View commit details
Showing with 29 additions and 19 deletions.
  1. +18 −11 mibuild/xilinx_vivado.py
  2. +11 −8 migen/fhdl/structure.py
29 changes: 18 additions & 11 deletions mibuild/xilinx_vivado.py
View file
Original file line number Diff line number Diff line change
@@ -42,19 +42,26 @@ def _build_xdc(named_sc, named_pc):
return r

def _build_files(device, sources, vincpaths, build_name):
tcl_contents = ""
tcl = []
for filename, language in sources:
tcl_contents += "add_files " + filename.replace("\\", "/") + "\n"
tcl.append("add_files " + filename.replace("\\", "/"))

tcl_contents += "read_xdc %s.xdc\n" %build_name
tcl_contents += "synth_design -top top -part %s -include_dirs {%s}\n" %(device, " ".join(vincpaths))
tcl_contents += "place_design\n"
tcl_contents += "route_design\n"
tcl_contents += "report_timing_summary -file %s_timing.rpt\n" %(build_name)
tcl_contents += "report_utilization -file %s_utilization.rpt\n" %(build_name)
tcl_contents += "write_bitstream -force %s.bit \n" %build_name
tcl_contents += "quit\n"
tools.write_to_file(build_name + ".tcl", tcl_contents)
tcl.append("read_xdc %s.xdc" %build_name)
tcl.append("synth_design -top top -part %s -include_dirs {%s}" %(device, " ".join(vincpaths)))
tcl.append("report_utilization -file %s_utilization_synth.rpt" %(build_name))
tcl.append("place_design")
tcl.append("report_utilization -file %s_utilization_place.rpt" %(build_name))
tcl.append("report_io -file %s_io.rpt" %(build_name))
tcl.append("report_control_sets -verbose -file %s_control_sets.rpt" %(build_name))
tcl.append("report_clock_utilization -file %s_clock_utilization.rpt" %(build_name))
tcl.append("route_design")
tcl.append("report_route_status -file %s_route_status.rpt" %(build_name))
tcl.append("report_drc -file %s_drc.rpt" %(build_name))
tcl.append("report_timing_summary -file %s_timing.rpt" %(build_name))
tcl.append("report_power -file %s_power.rpt" %(build_name))
tcl.append("write_bitstream -force %s.bit " %build_name)
tcl.append("quit")
tools.write_to_file(build_name + ".tcl", "\n".join(tcl))

def _run_vivado(build_name, vivado_path, source, ver=None):
if sys.platform == "win32" or sys.platform == "cygwin":
19 changes: 11 additions & 8 deletions migen/fhdl/structure.py
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,3 @@
import inspect
import re
import builtins
from collections import defaultdict

@@ -81,17 +79,20 @@ def __ge__(self, other):
def __getitem__(self, key):
from migen.fhdl.bitcontainer import flen

n = flen(self)
if isinstance(key, int):
if key >= n:
raise IndexError
if key < 0:
key += flen(self)
key += n
return _Slice(self, key, key+1)
elif isinstance(key, slice):
start, stop, step = key.indices(flen(self))
start, stop, step = key.indices(n)
if step != 1:
return Cat(self[i] for i in range(start, stop, step))
return _Slice(self, start, stop)
else:
raise KeyError
raise TypeError

def eq(self, r):
"""Assignment
@@ -275,7 +276,7 @@ def __repr__(self):
return "<Signal " + (self.backtrace[-1][0] or "anonymous") + " at " + hex(id(self)) + ">"

@classmethod
def like(cls, other):
def like(cls, other, **kwargs):
"""Create Signal based on another.
Parameters
@@ -286,7 +287,7 @@ def like(cls, other):
See `migen.fhdl.bitcontainer.value_bits_sign`() for details.
"""
from migen.fhdl.bitcontainer import value_bits_sign
return cls(value_bits_sign(other))
return cls(bits_sign=value_bits_sign(other), **kwargs)

class ClockSignal(Value):
"""Clock signal for a given clock domain
@@ -510,8 +511,10 @@ def __init__(self, name=None, reset_less=False):
self.name = tracer.get_obj_var_name(name)
if self.name is None:
raise ValueError("Cannot extract clock domain name from code, need to specify.")
if len(self.name) > 3 and self.name[:3] == "cd_":
if self.name.startswith("cd_"):
self.name = self.name[3:]
if self.name[0].isdigit():
raise ValueError("Clock domain name cannot start with a number.")
self.clk = Signal(name_override=self.name + "_clk")
if reset_less:
self.rst = None