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base repository: m-labs/migen
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  • 3 commits
  • 3 files changed
  • 2 contributors

Commits on Apr 22, 2015

  1. add Travis CI badge

    peteut authored and sbourdeauducq committed Apr 22, 2015
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    6b59697 View commit details
  2. test: add test for asic_syntax

    hutch31 authored and sbourdeauducq committed Apr 22, 2015
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    7ec0eca View commit details
  3. travis: install verilator

    hutch31 authored and sbourdeauducq committed Apr 22, 2015
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    e5b170f View commit details
Showing with 67 additions and 0 deletions.
  1. +3 −0 .travis.yml
  2. +6 −0 README.md
  3. +58 −0 migen/test/asic_syntax.py
3 changes: 3 additions & 0 deletions .travis.yml
Original file line number Diff line number Diff line change
@@ -10,6 +10,9 @@ install:
- "iverilog -v; true"
# Build the vpi module.
- "(cd vpi; make; sudo make install)"
# Install verilator package
- "sudo apt-get install verilator"
- "verilator --version; true"

script:
- "python setup.py test"
6 changes: 6 additions & 0 deletions README.md
Original file line number Diff line number Diff line change
@@ -1,4 +1,8 @@
### Migen (Milkymist generator)

[![Build Status](https://travis-ci.org/m-labs/migen.svg)](
https://travis-ci.org/m-labs/migen)

#### A Python toolbox for building complex digital hardware

Despite being faster than schematics entry, hardware design with Verilog and
@@ -41,6 +45,7 @@ Online documentation:
http://m-labs.hk/gateware.html

#### Quick intro

```python
from migen.fhdl.std import *
from mibuild.platforms import m1
@@ -54,6 +59,7 @@ plat.build_cmdline(m)
```

#### License

Migen is released under the very permissive two-clause BSD license. Under the
terms of this license, you are authorized to use Migen for closed-source
proprietary designs.
58 changes: 58 additions & 0 deletions migen/test/asic_syntax.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,58 @@
import unittest
import subprocess
import os

from migen.fhdl.std import *
from migen.fhdl.verilog import convert


# Create a module with some combinatorial, some sequential, and some simple assigns
class ThingBlock(Module):
def __init__(self):
x = [Signal(8) for y in range(10)]
y = [Signal(8) for z in range(10)]
en = Signal()
a = Signal()
b = Signal()
z = Signal()
as_src = Signal(16);
as_tgt1 = Signal(16);
as_tgt2 = Signal(16);
self.io = {a, b, z, en, as_src, as_tgt1, as_tgt2}

self.comb += If(a, z.eq(b))
self.comb += as_tgt1.eq(as_src)
self.comb += as_tgt2.eq(100)
for xi in x:
self.io.add(xi)
for xi in range(1, len(x)):
self.comb += If(en, y[xi].eq(x[xi-1])).Else(y[xi].eq(x[xi]))
self.sync += x[xi].eq(y[xi])


# Create unit test to build module, run Verilator and check for errors
class TestThingBlock(unittest.TestCase):
def test_mode_true(self):
filename = "test_module_true.v"
t = ThingBlock()
with open(filename, "w") as fh:
fh.write("/* verilator lint_off WIDTH */\n")
fh.write(str(convert(t, t.io, name="test_module",
asic_syntax=True)))

subprocess.check_call("verilator --lint-only " + filename,
stdout=subprocess.DEVNULL,
stderr=subprocess.DEVNULL, shell=True)
os.unlink(filename)

def test_mode_false(self):
filename = "test_module_false.v"
t = ThingBlock()
with open(filename, "w") as fh:
fh.write(str(convert(t, t.io, name="test_module")))

with self.assertRaises(subprocess.CalledProcessError):
subprocess.check_call("verilator --lint-only " + filename,
stdout=subprocess.DEVNULL,
stderr=subprocess.DEVNULL, shell=True)
os.unlink(filename)