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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: bc30fc57e7ea
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Apr 24, 2015

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    61c3efc View commit details
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Showing with 48 additions and 37 deletions.
  1. +23 −14 migen/fhdl/verilog.py
  2. +25 −23 migen/test/{asic_syntax.py → test_syntax.py}
37 changes: 23 additions & 14 deletions migen/fhdl/verilog.py
Original file line number Diff line number Diff line change
@@ -151,7 +151,8 @@ def _list_comb_wires(f):
return r


def _printheader(f, ios, name, ns, asic_syntax=False):
def _printheader(f, ios, name, ns,
reg_initialization=True):
sigs = list_signals(f) | list_special_ios(f, True, True, True)
special_outs = list_special_ios(f, False, True, True)
inouts = list_special_ios(f, False, False, True)
@@ -177,22 +178,25 @@ def _printheader(f, ios, name, ns, asic_syntax=False):
if sig in wires:
r += "wire " + _printsig(ns, sig) + ";\n"
else:
if asic_syntax:
r += "reg " + _printsig(ns, sig) + ";\n"
else:
if reg_initialization:
r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
else:
r += "reg " + _printsig(ns, sig) + ";\n"
r += "\n"
return r


def _printcomb(f, ns, display_run, asic_syntax=False):
def _printcomb(f, ns,
display_run=False,
dummy_signal=True,
blocking_assign=False):
r = ""
if f.comb:
# Generate a dummy event to get the simulator
# to run the combinatorial process once at the beginning.
syn_off = "// synthesis translate_off\n"
syn_on = "// synthesis translate_on\n"
if not asic_syntax:
if dummy_signal:
# Generate a dummy event to get the simulator
# to run the combinatorial process once at the beginning.
syn_off = "// synthesis translate_off\n"
syn_on = "// synthesis translate_on\n"
dummy_s = Signal(name_override="dummy_s")
r += syn_off
r += "reg " + _printsig(ns, dummy_s) + ";\n"
@@ -205,7 +209,7 @@ def _printcomb(f, ns, display_run, asic_syntax=False):
if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
r += "assign " + _printnode(ns, _AT_BLOCKING, 0, g[1][0])
else:
if not asic_syntax:
if dummy_signal:
dummy_d = Signal(name_override="dummy_d")
r += "\n" + syn_off
r += "reg " + _printsig(ns, dummy_d) + ";\n"
@@ -214,14 +218,15 @@ def _printcomb(f, ns, display_run, asic_syntax=False):
r += "always @(*) begin\n"
if display_run:
r += "\t$display(\"Running comb block #" + str(n) + "\");\n"
if asic_syntax:
if blocking_assign:
for t in g[0]:
r += "\t" + ns.get_name(t) + " = " + _printexpr(ns, t.reset)[0] + ";\n"
r += _printnode(ns, _AT_BLOCKING, 1, g[1])
else:
for t in g[0]:
r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n"
r += _printnode(ns, _AT_NONBLOCKING, 1, g[1])
if dummy_signal:
r += syn_off
r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
r += syn_on
@@ -323,8 +328,12 @@ def convert(f, ios=None, name="top",
r.ns = ns

src = "/* Machine-generated using Migen */\n"
src += _printheader(f, ios, name, ns, asic_syntax)
src += _printcomb(f, ns, display_run, asic_syntax)
src += _printheader(f, ios, name, ns,
reg_initialization=not asic_syntax)
src += _printcomb(f, ns,
display_run=display_run,
dummy_signal=not asic_syntax,
blocking_assign=asic_syntax)
src += _printsync(f, ns)
src += _printspecials(special_overrides, f.specials - lowered_specials, ns, r.add_data_file)
src += "endmodule\n"
48 changes: 25 additions & 23 deletions migen/test/asic_syntax.py → migen/test/test_syntax.py
Original file line number Diff line number Diff line change
@@ -6,8 +6,9 @@
from migen.fhdl.verilog import convert


# Create a module with some combinatorial, some sequential, and some simple assigns
class ThingBlock(Module):
# Create a module with some combinatorial, some sequential, and some simple
# assigns
class SyntaxModule(Module):
def __init__(self):
x = [Signal(8) for y in range(10)]
y = [Signal(8) for z in range(10)]
@@ -31,28 +32,29 @@ def __init__(self):


# Create unit test to build module, run Verilator and check for errors
class TestThingBlock(unittest.TestCase):
def test_mode_true(self):
filename = "test_module_true.v"
t = ThingBlock()
with open(filename, "w") as fh:
fh.write("/* verilator lint_off WIDTH */\n")
fh.write(str(convert(t, t.io, name="test_module",
asic_syntax=True)))

subprocess.check_call("verilator --lint-only " + filename,
class SyntaxCase(unittest.TestCase):
def base_test(self, name, asic_syntax, options=[]):
filename = "test_module_{}.v".format(name)
t = SyntaxModule()
c = convert(t, t.io, name="test_module", asic_syntax=asic_syntax)
f = open(filename, "w")
f.write(str(c))
f.close()
subprocess.check_call("verilator --lint-only " + " ".join(options) + " " + filename,
stdout=subprocess.DEVNULL,
stderr=subprocess.DEVNULL, shell=True)
os.unlink(filename)

def test_mode_false(self):
filename = "test_module_false.v"
t = ThingBlock()
with open(filename, "w") as fh:
fh.write(str(convert(t, t.io, name="test_module")))

with self.assertRaises(subprocess.CalledProcessError):
subprocess.check_call("verilator --lint-only " + filename,
stdout=subprocess.DEVNULL,
stderr=subprocess.DEVNULL, shell=True)
os.unlink(filename)
def test_generic_syntax(self):
options = [
"-Wno-WIDTH",
"-Wno-COMBDLY",
"-Wno-INITIALDLY"
]
self.base_test("generic", False, options)

def test_asic_syntax(self):
options = [
"-Wno-WIDTH", # XXX should we improve ASIC backend to remove this?
]
self.base_test("asic", True, options)