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  • 7 commits
  • 62 files changed
  • 1 contributor

Commits on Apr 27, 2015

  1. litesata: remove icarus_workaround.patch (obsolete)

    @enjoy-digital
    enjoy-digital committed Apr 27, 2015
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    fe867cc View commit details

  2. litesata: use new Migen modules from actorlib/packet.py (avoid duplic… 

    …ations between cores)
    @enjoy-digital
    enjoy-digital committed Apr 27, 2015
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    ded3f22 View commit details

  3. litesata: split hdd model (phy, link, transport, command & hdd) and u… 

    …pdate simulations
    @enjoy-digital
    enjoy-digital committed Apr 27, 2015
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    1ef81c4 View commit details

  4. litepcie: use new Migen modules from actorlib (avoid duplications bet… 

    …ween cores)
    @enjoy-digital
    enjoy-digital committed Apr 27, 2015
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    20dd6d3 View commit details

  5. liteeth: use new Migen modules from actorlib (avoid duplications betw… 

    …een cores)
    @enjoy-digital
    enjoy-digital committed Apr 27, 2015
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    91c77d4 View commit details

  6. liteusb: begin refactoring and simplification (wip)

    @enjoy-digital
    enjoy-digital committed Apr 27, 2015
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    dc8d844 View commit details

  7. Merge branch 'master' of https://github.com/m-labs/misoc

    @enjoy-digital
    enjoy-digital committed Apr 27, 2015
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    0c08055 View commit details
Showing with 899 additions and 1,272 deletions.
  1. +96 −94 misoclib/com/liteeth/common.py
  2. +4 −6 misoclib/com/liteeth/core/arp/__init__.py
  3. +0 −2 misoclib/com/liteeth/core/etherbone/__init__.py
  4. +4 −6 misoclib/com/liteeth/core/etherbone/packet.py
  5. +4 −6 misoclib/com/liteeth/core/etherbone/record.py
  6. +5 −7 misoclib/com/liteeth/core/icmp/__init__.py
  7. +2 −4 misoclib/com/liteeth/core/ip/__init__.py
  8. +3 −3 misoclib/com/liteeth/core/ip/checksum.py
  9. +4 −6 misoclib/com/liteeth/core/udp/__init__.py
  10. +1 −1 misoclib/com/liteeth/example_designs/targets/udp.py
  11. +0 −117 misoclib/com/liteeth/generic/__init__.py
  12. +0 −28 misoclib/com/liteeth/generic/arbiter.py
  13. +0 −2 misoclib/com/liteeth/generic/crossbar.py
  14. +4 −13 misoclib/com/liteeth/generic/depacketizer.py
  15. +0 −42 misoclib/com/liteeth/generic/dispatcher.py
  16. +5 −14 misoclib/com/liteeth/generic/packetizer.py
  17. +2 −4 misoclib/com/liteeth/mac/common.py
  18. +8 −8 misoclib/com/liteeth/test/model/arp.py
  19. +10 −10 misoclib/com/liteeth/test/model/etherbone.py
  20. +5 −5 misoclib/com/liteeth/test/model/icmp.py
  21. +7 −7 misoclib/com/liteeth/test/model/ip.py
  22. +5 −5 misoclib/com/liteeth/test/model/mac.py
  23. +7 −7 misoclib/com/liteeth/test/model/udp.py
  24. +2 −9 misoclib/com/litepcie/common.py
  25. +64 −64 misoclib/com/litepcie/core/packet/common.py
  26. +5 −15 misoclib/com/litepcie/core/packet/depacketizer.py
  27. +3 −13 misoclib/com/litepcie/core/packet/packetizer.py
  28. +0 −25 misoclib/com/litepcie/core/switch/arbiter.py
  29. +0 −2 misoclib/com/litepcie/core/switch/crossbar.py
  30. +0 −40 misoclib/com/litepcie/core/switch/dispatcher.py
  31. 0 misoclib/com/{liteusb/software/.keep_me → litepcie/test/model/__init__.py}
  32. +3 −3 misoclib/com/litepcie/test/model/host.py
  33. +7 −7 misoclib/com/litepcie/test/model/tlp.py
  34. 0 misoclib/com/liteusb/{test/.keep_me → __init__.py}
  35. +3 −40 misoclib/com/liteusb/common.py
  36. +11 −11 misoclib/com/liteusb/core/crc.py
  37. +13 −9 misoclib/com/liteusb/core/depacketizer.py
  38. +4 −4 misoclib/com/liteusb/core/packetizer.py
  39. +2 −15 misoclib/com/liteusb/frontend/crossbar.py
  40. +1 −1 misoclib/com/liteusb/frontend/dma.py
  41. +2 −2 misoclib/com/liteusb/frontend/uart.py
  42. 0 misoclib/com/liteusb/phy/__init__.py
  43. +4 −170 misoclib/com/liteusb/phy/ft2232h.py
  44. +7 −0 misoclib/com/liteusb/test/Makefile
  45. 0 misoclib/com/liteusb/test/__init__.py
  46. +16 −0 misoclib/com/liteusb/test/common.py
  47. +133 −0 misoclib/com/liteusb/test/ft2232h_tb.py
  48. +63 −166 misoclib/mem/litesata/common.py
  49. +2 −2 misoclib/mem/litesata/core/link/__init__.py
  50. +18 −45 misoclib/mem/litesata/core/transport/__init__.py
  51. +0 −131 misoclib/mem/litesata/icarus_workaround.patch
  52. 0 misoclib/mem/litesata/test/__init__.py
  53. +1 −1 misoclib/mem/litesata/test/bist_tb.py
  54. +1 −1 misoclib/mem/litesata/test/command_tb.py
  55. +7 −0 misoclib/mem/litesata/test/common.py
  56. +1 −1 misoclib/mem/litesata/test/link_tb.py
  57. 0 misoclib/mem/litesata/test/model/__init__.py
  58. +28 −0 misoclib/mem/litesata/test/model/command.py
  59. +97 −0 misoclib/mem/litesata/test/model/hdd.py
  60. +11 −98 misoclib/mem/litesata/test/{hdd.py → model/link.py}
  61. +77 −0 misoclib/mem/litesata/test/model/phy.py
  62. +137 −0 misoclib/mem/litesata/test/model/transport.py
190 changes: 96 additions & 94 deletions misoclib/com/liteeth/common.py
View file
Original file line number Diff line number Diff line change
@@ -5,11 +5,11 @@
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.record import *
from migen.genlib.fsm import FSM, NextState
from migen.genlib.misc import chooser, FlipFlop, Counter, Timeout
from migen.genlib.misc import chooser, reverse_bytes, FlipFlop, Counter, Timeout
from migen.flow.actor import *
from migen.flow.plumbing import Buffer
from migen.actorlib.structuring import Converter, Pipeline
from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
from migen.actorlib.packet import *
from migen.bank.description import *

eth_mtu = 1532
@@ -18,121 +18,123 @@
eth_preamble = 0xD555555555555555
buffer_depth = 2**log2_int(eth_mtu, need_pow2=False)


class HField():
def __init__(self, byte, offset, width):
self.byte = byte
self.offset = offset
self.width = width

ethernet_type_ip = 0x800
ethernet_type_arp = 0x806

mac_header_len = 14
mac_header = {
"target_mac": HField(0, 0, 48),
"sender_mac": HField(6, 0, 48),
"ethernet_type": HField(12, 0, 16)
mac_header_length = 14
mac_header_fields = {
"target_mac": HeaderField(0, 0, 48),
"sender_mac": HeaderField(6, 0, 48),
"ethernet_type": HeaderField(12, 0, 16)
}
mac_header = Header(mac_header_fields,
mac_header_length,
swap_field_bytes=True)

arp_hwtype_ethernet = 0x0001
arp_proto_ip = 0x0800
arp_opcode_request = 0x0001
arp_opcode_reply = 0x0002

arp_header_len = 28
arp_header = {
"hwtype": HField(0, 0, 16),
"proto": HField(2, 0, 16),
"hwsize": HField(4, 0, 8),
"protosize": HField(5, 0, 8),
"opcode": HField(6, 0, 16),
"sender_mac": HField(8, 0, 48),
"sender_ip": HField(14, 0, 32),
"target_mac": HField(18, 0, 48),
"target_ip": HField(24, 0, 32)
arp_header_length = 28
arp_header_fields = {
"hwtype": HeaderField(0, 0, 16),
"proto": HeaderField(2, 0, 16),
"hwsize": HeaderField(4, 0, 8),
"protosize": HeaderField(5, 0, 8),
"opcode": HeaderField(6, 0, 16),
"sender_mac": HeaderField(8, 0, 48),
"sender_ip": HeaderField(14, 0, 32),
"target_mac": HeaderField(18, 0, 48),
"target_ip": HeaderField(24, 0, 32)
}

ipv4_header_len = 20
ipv4_header = {
"ihl": HField(0, 0, 4),
"version": HField(0, 4, 4),
"total_length": HField(2, 0, 16),
"identification": HField(4, 0, 16),
"ttl": HField(8, 0, 8),
"protocol": HField(9, 0, 8),
"checksum": HField(10, 0, 16),
"sender_ip": HField(12, 0, 32),
"target_ip": HField(16, 0, 32)
arp_header = Header(arp_header_fields,
arp_header_length,
swap_field_bytes=True)


ipv4_header_length = 20
ipv4_header_fields = {
"ihl": HeaderField(0, 0, 4),
"version": HeaderField(0, 4, 4),
"total_length": HeaderField(2, 0, 16),
"identification": HeaderField(4, 0, 16),
"ttl": HeaderField(8, 0, 8),
"protocol": HeaderField(9, 0, 8),
"checksum": HeaderField(10, 0, 16),
"sender_ip": HeaderField(12, 0, 32),
"target_ip": HeaderField(16, 0, 32)
}
ipv4_header = Header(ipv4_header_fields,
ipv4_header_length,
swap_field_bytes=True)

icmp_header_len = 8
icmp_header = {
"msgtype": HField(0, 0, 8),
"code": HField(1, 0, 8),
"checksum": HField(2, 0, 16),
"quench": HField(4, 0, 32)
}
icmp_protocol = 0x01

udp_header_len = 8
udp_header = {
"src_port": HField(0, 0, 16),
"dst_port": HField(2, 0, 16),
"length": HField(4, 0, 16),
"checksum": HField(6, 0, 16)
icmp_header_length = 8
icmp_header_fields = {
"msgtype": HeaderField(0, 0, 8),
"code": HeaderField(1, 0, 8),
"checksum": HeaderField(2, 0, 16),
"quench": HeaderField(4, 0, 32)
}
icmp_header = Header(icmp_header_fields,
icmp_header_length,
swap_field_bytes=True)

udp_protocol = 0x11

udp_header_length = 8
udp_header_fields = {
"src_port": HeaderField(0, 0, 16),
"dst_port": HeaderField(2, 0, 16),
"length": HeaderField(4, 0, 16),
"checksum": HeaderField(6, 0, 16)
}
udp_header = Header(udp_header_fields,
udp_header_length,
swap_field_bytes=True)


etherbone_magic = 0x4e6f
etherbone_version = 1
etherbone_packet_header_len = 8
etherbone_packet_header = {
"magic": HField(0, 0, 16),
etherbone_packet_header_length = 8
etherbone_packet_header_fields = {
"magic": HeaderField(0, 0, 16),

"version": HField(2, 4, 4),
"nr": HField(2, 2, 1),
"pr": HField(2, 1, 1),
"pf": HField(2, 0, 1),
"version": HeaderField(2, 4, 4),
"nr": HeaderField(2, 2, 1),
"pr": HeaderField(2, 1, 1),
"pf": HeaderField(2, 0, 1),

"addr_size": HField(3, 4, 4),
"port_size": HField(3, 0, 4)
"addr_size": HeaderField(3, 4, 4),
"port_size": HeaderField(3, 0, 4)
}
etherbone_packet_header = Header(etherbone_packet_header_fields,
etherbone_packet_header_length,
swap_field_bytes=True)

etherbone_record_header_len = 4
etherbone_record_header = {
"bca": HField(0, 0, 1),
"rca": HField(0, 1, 1),
"rff": HField(0, 2, 1),
"cyc": HField(0, 4, 1),
"wca": HField(0, 5, 1),
"wff": HField(0, 6, 1),
etherbone_record_header_length = 4
etherbone_record_header_fields = {
"bca": HeaderField(0, 0, 1),
"rca": HeaderField(0, 1, 1),
"rff": HeaderField(0, 2, 1),
"cyc": HeaderField(0, 4, 1),
"wca": HeaderField(0, 5, 1),
"wff": HeaderField(0, 6, 1),

"byte_enable": HField(1, 0, 8),
"byte_enable": HeaderField(1, 0, 8),

"wcount": HField(2, 0, 8),
"wcount": HeaderField(2, 0, 8),

"rcount": HField(3, 0, 8)
"rcount": HeaderField(3, 0, 8)
}


def reverse_bytes(v):
n = math.ceil(flen(v)/8)
r = []
for i in reversed(range(n)):
r.append(v[i*8:min((i+1)*8, flen(v))])
return Cat(iter(r))
etherbone_record_header = Header(etherbone_record_header_fields,
etherbone_record_header_length,
swap_field_bytes=True)


# layouts
def _layout_from_header(header):
_layout = []
for k, v in sorted(header.items()):
_layout.append((k, v.width))
return _layout


def _remove_from_layout(layout, *args):
r = []
for f in layout:
@@ -155,7 +157,7 @@ def eth_phy_description(dw):


def eth_mac_description(dw):
payload_layout = _layout_from_header(mac_header) + [
payload_layout = mac_header.get_layout() + [
("data", dw),
("last_be", dw//8),
("error", dw//8)
@@ -164,7 +166,7 @@ def eth_mac_description(dw):


def eth_arp_description(dw):
param_layout = _layout_from_header(arp_header)
param_layout = arp_header.get_layout()
payload_layout = [
("data", dw),
("error", dw//8)
@@ -182,7 +184,7 @@ def eth_arp_description(dw):


def eth_ipv4_description(dw):
param_layout = _layout_from_header(ipv4_header)
param_layout = ipv4_header.get_layout()
payload_layout = [
("data", dw),
("error", dw//8)
@@ -212,7 +214,7 @@ def convert_ip(s):


def eth_icmp_description(dw):
param_layout = _layout_from_header(icmp_header)
param_layout = icmp_header.get_layout()
payload_layout = [
("data", dw),
("error", dw//8)
@@ -221,7 +223,7 @@ def eth_icmp_description(dw):


def eth_icmp_user_description(dw):
param_layout = _layout_from_header(icmp_header) + [
param_layout = icmp_header.get_layout() + [
("ip_address", 32),
("length", 16)
]
@@ -233,7 +235,7 @@ def eth_icmp_user_description(dw):


def eth_udp_description(dw):
param_layout = _layout_from_header(udp_header)
param_layout = udp_header.get_layout()
payload_layout = [
("data", dw),
("error", dw//8)
@@ -256,7 +258,7 @@ def eth_udp_user_description(dw):


def eth_etherbone_packet_description(dw):
param_layout = _layout_from_header(etherbone_packet_header)
param_layout = etherbone_packet_header.get_layout()
payload_layout = [
("data", dw),
("error", dw//8)
@@ -265,7 +267,7 @@ def eth_etherbone_packet_description(dw):


def eth_etherbone_packet_user_description(dw):
param_layout = _layout_from_header(etherbone_packet_header)
param_layout = etherbone_packet_header.get_layout()
param_layout = _remove_from_layout(param_layout,
"magic",
"portsize",
@@ -280,7 +282,7 @@ def eth_etherbone_packet_user_description(dw):


def eth_etherbone_record_description(dw):
param_layout = _layout_from_header(etherbone_record_header)
param_layout = etherbone_record_header.get_layout()
payload_layout = [
("data", dw),
("error", dw//8)
10 changes: 4 additions & 6 deletions misoclib/com/liteeth/core/arp/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -16,8 +16,7 @@ def __init__(self):
LiteEthPacketizer.__init__(self,
eth_arp_description(8),
eth_mac_description(8),
arp_header,
arp_header_len)
arp_header)


class LiteEthARPTX(Module):
@@ -29,7 +28,7 @@ def __init__(self, mac_address, ip_address):

self.submodules.packetizer = packetizer = LiteEthARPPacketizer()

counter = Counter(max=max(arp_header_len, eth_min_len))
counter = Counter(max=max(arp_header.length, eth_min_len))
self.submodules += counter

self.submodules.fsm = fsm = FSM(reset_state="IDLE")
@@ -43,7 +42,7 @@ def __init__(self, mac_address, ip_address):
)
self.comb += [
packetizer.sink.sop.eq(counter.value == 0),
packetizer.sink.eop.eq(counter.value == max(arp_header_len, eth_min_len)-1),
packetizer.sink.eop.eq(counter.value == max(arp_header.length, eth_min_len)-1),
packetizer.sink.hwtype.eq(arp_hwtype_ethernet),
packetizer.sink.proto.eq(arp_proto_ip),
packetizer.sink.hwsize.eq(6),
@@ -82,8 +81,7 @@ def __init__(self):
LiteEthDepacketizer.__init__(self,
eth_mac_description(8),
eth_arp_description(8),
arp_header,
arp_header_len)
arp_header)


class LiteEthARPRX(Module):
2 changes: 0 additions & 2 deletions misoclib/com/liteeth/core/etherbone/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,5 @@
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
from misoclib.com.liteeth.generic.arbiter import Arbiter
from misoclib.com.liteeth.generic.dispatcher import Dispatcher
from misoclib.com.liteeth.core.etherbone.packet import *
from misoclib.com.liteeth.core.etherbone.probe import *
from misoclib.com.liteeth.core.etherbone.record import *
10 changes: 4 additions & 6 deletions misoclib/com/liteeth/core/etherbone/packet.py
View file
Original file line number Diff line number Diff line change
@@ -9,8 +9,7 @@ def __init__(self):
LiteEthPacketizer.__init__(self,
eth_etherbone_packet_description(32),
eth_udp_user_description(32),
etherbone_packet_header,
etherbone_packet_header_len)
etherbone_packet_header)


class LiteEthEtherbonePacketTX(Module):
@@ -50,7 +49,7 @@ def __init__(self, udp_port):
source.src_port.eq(udp_port),
source.dst_port.eq(udp_port),
source.ip_address.eq(sink.ip_address),
source.length.eq(sink.length + etherbone_packet_header_len),
source.length.eq(sink.length + etherbone_packet_header.length),
If(source.stb & source.eop & source.ack,
NextState("IDLE")
)
@@ -62,8 +61,7 @@ def __init__(self):
LiteEthDepacketizer.__init__(self,
eth_udp_user_description(32),
eth_etherbone_packet_description(32),
etherbone_packet_header,
etherbone_packet_header_len)
etherbone_packet_header)


class LiteEthEtherbonePacketRX(Module):
@@ -109,7 +107,7 @@ def __init__(self):
source.src_port.eq(sink.src_port),
source.dst_port.eq(sink.dst_port),
source.ip_address.eq(sink.ip_address),
source.length.eq(sink.length - etherbone_packet_header_len)
source.length.eq(sink.length - etherbone_packet_header.length)
]
fsm.act("PRESENT",
source.stb.eq(depacketizer.source.stb),
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