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lite*: adapt to new ModuleTransformer semantics
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NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
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jordens authored and sbourdeauducq committed Apr 4, 2015
1 parent 2583e97 commit 66f8dcb
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Showing 4 changed files with 12 additions and 11 deletions.
1 change: 0 additions & 1 deletion misoclib/com/liteeth/common.py
Expand Up @@ -2,7 +2,6 @@
from collections import OrderedDict

from migen.fhdl.std import *
from migen.fhdl.decorators import ModuleDecorator
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.record import *
from migen.genlib.fsm import FSM, NextState
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10 changes: 6 additions & 4 deletions misoclib/com/liteeth/generic/__init__.py
@@ -1,3 +1,4 @@
from migen.fhdl.decorators import ModuleTransformer
from misoclib.com.liteeth.common import *

# Generic classes
Expand All @@ -10,15 +11,16 @@ def connect(self, port):
return r

# Generic modules
class BufferizeEndpoints(ModuleDecorator):
def __init__(self, submodule, *args):
ModuleDecorator.__init__(self, submodule)
class BufferizeEndpoints(ModuleTransformer):
def __init__(self, *names):
self.names = names

def transform_instance(self, submodule):
endpoints = get_endpoints(submodule)
sinks = {}
sources = {}
for name, endpoint in endpoints.items():
if name in args or len(args) == 0:
if not self.names or name in self.names:
if isinstance(endpoint, Sink):
sinks.update({name : endpoint})
elif isinstance(endpoint, Source):
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11 changes: 6 additions & 5 deletions misoclib/mem/litesata/common.py
@@ -1,7 +1,7 @@
import math

from migen.fhdl.std import *
from migen.fhdl.decorators import ModuleDecorator
from migen.fhdl.decorators import ModuleTransformer
from migen.genlib.resetsync import *
from migen.genlib.fsm import *
from migen.genlib.record import *
Expand Down Expand Up @@ -252,15 +252,16 @@ def sectors2dwords(n):
return n*logical_sector_size//4

# Generic modules
class BufferizeEndpoints(ModuleDecorator):
def __init__(self, submodule, *args):
ModuleDecorator.__init__(self, submodule)
class BufferizeEndpoints(ModuleTransformer):
def __init__(self, *names):
self.names = names

def transform_instance(self, submodule):
endpoints = get_endpoints(submodule)
sinks = {}
sources = {}
for name, endpoint in endpoints.items():
if name in args or len(args) == 0:
if not self.names or name in self.names:
if isinstance(endpoint, Sink):
sinks.update({name : endpoint})
elif isinstance(endpoint, Source):
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1 change: 0 additions & 1 deletion misoclib/mem/litesata/frontend/bist.py
@@ -1,7 +1,6 @@
from misoclib.mem.litesata.common import *
from misoclib.mem.litesata.core.link.scrambler import Scrambler

from migen.fhdl.decorators import ModuleDecorator
from migen.bank.description import *

class LiteSATABISTGenerator(Module):
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