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base repository: m-labs/migen
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compare: aac953dd9035
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  • 3 commits
  • 1 file changed
  • 1 contributor

Commits on Apr 4, 2015

  1. vivado: make _build_files() a method and rename

    @jordens @sbourdeauducq
    jordens authored and sbourdeauducq committed Apr 4, 2015
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    4522956 View commit details

  2. vivado: add support for pre_synthesis_commands

    @jordens @sbourdeauducq
    jordens authored and sbourdeauducq committed Apr 4, 2015
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    9506f69 View commit details

  3. vivado: support phys_opt

    @jordens @sbourdeauducq
    jordens authored and sbourdeauducq committed Apr 4, 2015
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    aac953d View commit details
Showing with 34 additions and 30 deletions.
  1. +34 −30 mibuild/xilinx/vivado.py
64 changes: 34 additions & 30 deletions mibuild/xilinx/vivado.py
View file
Original file line number Diff line number Diff line change
@@ -46,34 +46,6 @@ def _build_xdc(named_sc, named_pc):
r += "\n" + "\n\n".join(named_pc)
return r

def _build_files(device, sources, vincpaths, build_name, bitstream_commands, additional_commands):
tcl = []
for filename, language in sources:
tcl.append("add_files " + filename.replace("\\", "/"))

tcl.append("read_xdc %s.xdc" %build_name)
tcl.append("synth_design -top top -part %s -include_dirs {%s}" %(device, " ".join(vincpaths)))
tcl.append("report_utilization -hierarchical -file %s_utilization_hierarchical_synth.rpt" %(build_name))
tcl.append("report_utilization -file %s_utilization_synth.rpt" %(build_name))
tcl.append("place_design")
tcl.append("report_utilization -hierarchical -file %s_utilization_hierarchical_place.rpt" %(build_name))
tcl.append("report_utilization -file %s_utilization_place.rpt" %(build_name))
tcl.append("report_io -file %s_io.rpt" %(build_name))
tcl.append("report_control_sets -verbose -file %s_control_sets.rpt" %(build_name))
tcl.append("report_clock_utilization -file %s_clock_utilization.rpt" %(build_name))
tcl.append("route_design")
tcl.append("report_route_status -file %s_route_status.rpt" %(build_name))
tcl.append("report_drc -file %s_drc.rpt" %(build_name))
tcl.append("report_timing_summary -max_paths 10 -file %s_timing.rpt" %(build_name))
tcl.append("report_power -file %s_power.rpt" %(build_name))
for bitstream_command in bitstream_commands:
tcl.append(bitstream_command.format(build_name=build_name))
tcl.append("write_bitstream -force %s.bit " %build_name)
for additional_command in additional_commands:
tcl.append(additional_command.format(build_name=build_name))
tcl.append("quit")
tools.write_to_file(build_name + ".tcl", "\n".join(tcl))

def _run_vivado(build_name, vivado_path, source, ver=None):
if sys.platform == "win32" or sys.platform == "cygwin":
build_script_contents = "REM Autogenerated by mibuild\n"
@@ -97,6 +69,39 @@ class XilinxVivadoToolchain:
def __init__(self):
self.bitstream_commands = []
self.additional_commands = []
self.pre_synthesis_commands = []
self.with_phys_opt = False

def _build_batch(self, platform, sources, build_name):
tcl = []
for filename, language in sources:
tcl.append("add_files " + filename.replace("\\", "/"))

tcl.append("read_xdc %s.xdc" %build_name)
tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
tcl.append("synth_design -top top -part %s -include_dirs {%s}" %(platform.device, " ".join(platform.verilog_include_paths)))
tcl.append("report_utilization -hierarchical -file %s_utilization_hierarchical_synth.rpt" %(build_name))
tcl.append("report_utilization -file %s_utilization_synth.rpt" %(build_name))
tcl.append("place_design")
if self.with_phys_opt:
tcl.append("phys_opt_design -directive AddRetime")
tcl.append("report_utilization -hierarchical -file %s_utilization_hierarchical_place.rpt" %(build_name))
tcl.append("report_utilization -file %s_utilization_place.rpt" %(build_name))
tcl.append("report_io -file %s_io.rpt" %(build_name))
tcl.append("report_control_sets -verbose -file %s_control_sets.rpt" %(build_name))
tcl.append("report_clock_utilization -file %s_clock_utilization.rpt" %(build_name))
tcl.append("route_design")
tcl.append("report_route_status -file %s_route_status.rpt" %(build_name))
tcl.append("report_drc -file %s_drc.rpt" %(build_name))
tcl.append("report_timing_summary -max_paths 10 -file %s_timing.rpt" %(build_name))
tcl.append("report_power -file %s_power.rpt" %(build_name))
for bitstream_command in self.bitstream_commands:
tcl.append(bitstream_command.format(build_name=build_name))
tcl.append("write_bitstream -force %s.bit " %build_name)
for additional_command in self.additional_commands:
tcl.append(additional_command.format(build_name=build_name))
tcl.append("quit")
tools.write_to_file(build_name + ".tcl", "\n".join(tcl))

def build(self, platform, fragment, build_dir="build", build_name="top",
vivado_path="/opt/Xilinx/Vivado", source=True, run=True):
@@ -111,8 +116,7 @@ def build(self, platform, fragment, build_dir="build", build_name="top",
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = platform.sources | {(v_file, "verilog")}
_build_files(platform.device, sources, platform.verilog_include_paths, build_name,
self.bitstream_commands, self.additional_commands)
self._build_batch(platform, sources, build_name)
tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
if run:
_run_vivado(build_name, vivado_path, source)