mibuild: support multiple specifications of include file and sources

m-labs · Apr 4, 2015 · 1d11895 · 1d11895
1 parent 357c807
commit 1d11895
Show file tree

Hide file tree

Showing 4 changed files with 7 additions and 7 deletions.
diff --git a/mibuild/altera/quartus.py b/mibuild/altera/quartus.py
@@ -85,7 +85,7 @@ def build(self, platform, fragment, build_dir="build", build_name="top",
 		named_sc, named_pc = platform.resolve_signals(vns)
 		v_file = build_name + ".v"
 		tools.write_to_file(v_file, v_src)
-		sources = platform.sources + [(v_file, "verilog")]
+		sources = platform.sources | {(v_file, "verilog")}
 		_build_files(platform.device, sources, platform.verilog_include_paths, named_sc, named_pc, build_name)
 		if run:
 			_run_quartus(build_name, quartus_path)

diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py
@@ -184,8 +184,8 @@ def __init__(self, device, io, connectors=[], name=None):
 		if name is None:
 			name = self.__module__.split(".")[-1]
 		self.name = name
-		self.sources = []
-		self.verilog_include_paths = []
+		self.sources = set()
+		self.verilog_include_paths = set()
 		self.finalized = False
 
 	def request(self, *args, **kwargs):
@@ -229,7 +229,7 @@ def add_source(self, filename, language=None):
 		if language is None:
 			language = "verilog" # default to Verilog
 		filename = os.path.abspath(filename)
-		self.sources.append((filename, language))
+		self.sources.add((filename, language))
 
 	def add_sources(self, path, *filenames, language=None):
 		for f in filenames:
@@ -251,7 +251,7 @@ def add_source_dir(self, path, recursive=True):
 				self.add_source(filename, language)
 
 	def add_verilog_include_path(self, path):
-		self.verilog_include_paths.append(os.path.abspath(path))
+		self.verilog_include_paths.add(os.path.abspath(path))
 
 	def resolve_signals(self, vns):
 		# resolve signal names in constraints

diff --git a/mibuild/xilinx/ise.py b/mibuild/xilinx/ise.py
@@ -149,7 +149,7 @@ def build(self, platform, fragment, build_dir="build", build_name="top",
 			named_sc, named_pc = platform.resolve_signals(vns)
 			v_file = build_name + ".v"
 			tools.write_to_file(v_file, v_src)
-			sources = platform.sources + [(v_file, "verilog")]
+			sources = platform.sources | {(v_file, "verilog")}
 			if mode == "xst":
 				_build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt)
 				isemode = "xst"

diff --git a/mibuild/xilinx/vivado.py b/mibuild/xilinx/vivado.py
@@ -110,7 +110,7 @@ def build(self, platform, fragment, build_dir="build", build_name="top",
 		named_sc, named_pc = platform.resolve_signals(vns)
 		v_file = build_name + ".v"
 		tools.write_to_file(v_file, v_src)
-		sources = platform.sources + [(v_file, "verilog")]
+		sources = platform.sources | {(v_file, "verilog")}
 		_build_files(platform.device, sources, platform.verilog_include_paths, build_name,
 			self.bitstream_commands, self.additional_commands)
 		tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))