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Commit 93ed321

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committedApr 10, 2015
timer: revert prescaler (we will in fact use a software prescaler for uIP)
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-19
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Diff for: ‎misoclib/cpu/peripherals/timer/__init__.py

+3-19
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,12 @@
11
from migen.fhdl.std import *
22
from migen.bank.description import *
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from migen.bank.eventmanager import *
4-
from migen.genlib.misc import Counter
54

65
class Timer(Module, AutoCSR):
7-
def __init__(self, width=32, prescaler_width=32):
6+
def __init__(self, width=32):
87
self._load = CSRStorage(width)
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self._reload = CSRStorage(width)
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self._en = CSRStorage()
11-
self._prescaler = CSRStorage(prescaler_width, reset=1)
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self._update_value = CSR()
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self._value = CSRStatus(width)
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@@ -17,28 +15,14 @@ def __init__(self, width=32, prescaler_width=32):
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self.ev.finalize()
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1917
###
20-
enable = self._en.storage
21-
tick = Signal()
22-
23-
counter = Counter(prescaler_width)
24-
self.submodules += counter
25-
self.comb += [
26-
If(enable,
27-
tick.eq(counter.value >= (self._prescaler.storage-1)),
28-
counter.ce.eq(1),
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counter.reset.eq(tick),
30-
).Else(
31-
counter.reset.eq(1)
32-
)
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]
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3519
value = Signal(width)
3620
self.sync += [
37-
If(enable,
21+
If(self._en.storage,
3822
If(value == 0,
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# set reload to 0 to disable reloading
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value.eq(self._reload.storage)
41-
).Elif(tick,
25+
).Else(
4226
value.eq(value - 1)
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)
4428
).Else(

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