pipistrello: add double-cpu

m-labs · Apr 5, 2015 · ef375b5 · sbourdeauducq · Apr 5, 2015 · jordens
1 parent c98e24a
commit ef375b5
Showing 1 changed file with 24 additions and 1 deletion.
diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py
@@ -7,7 +7,7 @@
 from misoclib.soc import mem_decoder
 from targets.pipistrello import BaseSoC
 
-from artiq.gateware import rtio, ad9858
+from artiq.gateware import amp, rtio, ad9858
 
 
 _tester_io = [
@@ -140,4 +140,27 @@ def __init__(self, platform, **kwargs):
         self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
 
 
+class Double(_QcAdapterBase):
+    csr_map = {
+        "kernel_cpu": 14
+    }
+    csr_map.update(_QcAdapterBase.csr_map)
+
+    def __init__(self, platform, *args, **kwargs):
+        _QcAdapterBase.__init__(self, platform, **kwargs)
+
+        self.submodules.kernel_cpu = amp.KernelCPU(
+            platform, self.sdram.crossbar.get_master())
+        self.submodules.mailbox = amp.Mailbox()
+        self.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i1)
+        self.kernel_cpu.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i2)
+
+        rtio_csrs = self.rtio.get_csrs()
+        self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
+        self.kernel_cpu.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
+        self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
+
+        self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
+
+
 default_subtarget = Single