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enjoy-digitalenjoy-digital
committedApr 2, 2015
remove use of _r prefix on CSRs
·
0.120.1
1 parent 696819c commit b437dc3

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9 files changed

+66
-66
lines changed

9 files changed

+66
-66
lines changed
 

Diff for: ‎misoclib/tools/litescope/frontend/io.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,8 @@
33
class LiteScopeIO(Module, AutoCSR):
44
def __init__(self, dw):
55
self.dw = dw
6-
self._r_i = CSRStatus(dw)
7-
self._r_o = CSRStorage(dw)
6+
self._i = CSRStatus(dw)
7+
self._o = CSRStorage(dw)
88

9-
self.i = self._r_i.status
10-
self.o = self._r_o.storage
9+
self.i = self._i.status
10+
self.o = self._o.storage

Diff for: ‎misoclib/video/dvisampler/analysis.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -120,7 +120,7 @@ def __init__(self, word_width):
120120
self.frame = Source(word_layout)
121121
self.busy = Signal()
122122

123-
self._r_overflow = CSR()
123+
self._overflow = CSR()
124124

125125
###
126126

@@ -194,11 +194,11 @@ def __init__(self, word_width):
194194

195195
overflow_mask = Signal()
196196
self.comb += [
197-
self._r_overflow.w.eq(sys_overflow & ~overflow_mask),
198-
self.overflow_reset.i.eq(self._r_overflow.re)
197+
self._overflow.w.eq(sys_overflow & ~overflow_mask),
198+
self.overflow_reset.i.eq(self._overflow.re)
199199
]
200200
self.sync += \
201-
If(self._r_overflow.re,
201+
If(self._overflow.re,
202202
overflow_mask.eq(1)
203203
).Elif(self.overflow_reset_ack.o,
204204
overflow_mask.eq(0)

Diff for: ‎misoclib/video/dvisampler/chansync.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ def __init__(self, nchan=3, depth=8):
4242
self.valid_i = Signal()
4343
self.chan_synced = Signal()
4444

45-
self._r_channels_synced = CSRStatus()
45+
self._channels_synced = CSRStatus()
4646

4747
lst_control = []
4848
all_control = Signal()
@@ -85,7 +85,7 @@ def __init__(self, nchan=3, depth=8):
8585
)
8686
)
8787
)
88-
self.specials += MultiReg(self.chan_synced, self._r_channels_synced.status)
88+
self.specials += MultiReg(self.chan_synced, self._channels_synced.status)
8989

9090
class _TB(Module):
9191
def __init__(self, test_seq_it):

Diff for: ‎misoclib/video/dvisampler/charsync.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@ def __init__(self, required_controls=8):
1111
self.synced = Signal()
1212
self.data = Signal(10)
1313

14-
self._r_char_synced = CSRStatus()
15-
self._r_ctl_pos = CSRStatus(bits_for(9))
14+
self._char_synced = CSRStatus()
15+
self._ctl_pos = CSRStatus(bits_for(9))
1616

1717
###
1818

@@ -47,7 +47,7 @@ def __init__(self, required_controls=8):
4747
),
4848
previous_control_position.eq(control_position)
4949
]
50-
self.specials += MultiReg(self.synced, self._r_char_synced.status)
51-
self.specials += MultiReg(word_sel, self._r_ctl_pos.status)
50+
self.specials += MultiReg(self.synced, self._char_synced.status)
51+
self.specials += MultiReg(word_sel, self._ctl_pos.status)
5252

5353
self.sync.pix += self.data.eq(raw >> word_sel)

Diff for: ‎misoclib/video/dvisampler/clocking.py

+18-18
Original file line numberDiff line numberDiff line change
@@ -4,16 +4,16 @@
44

55
class Clocking(Module, AutoCSR):
66
def __init__(self, pads):
7-
self._r_pll_reset = CSRStorage(reset=1)
8-
self._r_locked = CSRStatus()
7+
self._pll_reset = CSRStorage(reset=1)
8+
self._locked = CSRStatus()
99

1010
# DRP
11-
self._r_pll_adr = CSRStorage(5)
12-
self._r_pll_dat_r = CSRStatus(16)
13-
self._r_pll_dat_w = CSRStorage(16)
14-
self._r_pll_read = CSR()
15-
self._r_pll_write = CSR()
16-
self._r_pll_drdy = CSRStatus()
11+
self._pll_adr = CSRStorage(5)
12+
self._pll_dat_r = CSRStatus(16)
13+
self._pll_dat_w = CSRStorage(16)
14+
self._pll_read = CSR()
15+
self._pll_write = CSR()
16+
self._pll_drdy = CSRStatus()
1717

1818
self.locked = Signal()
1919
self.serdesstrobe = Signal()
@@ -32,10 +32,10 @@ def __init__(self, pads):
3232
pll_clk1 = Signal()
3333
pll_clk2 = Signal()
3434
pll_drdy = Signal()
35-
self.sync += If(self._r_pll_read.re | self._r_pll_write.re,
36-
self._r_pll_drdy.status.eq(0)
35+
self.sync += If(self._pll_read.re | self._pll_write.re,
36+
self._pll_drdy.status.eq(0)
3737
).Elif(pll_drdy,
38-
self._r_pll_drdy.status.eq(1)
38+
self._pll_drdy.status.eq(1)
3939
)
4040
self.specials += Instance("PLL_ADV",
4141
p_CLKFBOUT_MULT=10,
@@ -48,13 +48,13 @@ def __init__(self, pads):
4848
i_CLKIN1=clk_se,
4949
o_CLKOUT0=pll_clk0, o_CLKOUT1=pll_clk1, o_CLKOUT2=pll_clk2,
5050
o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbout,
51-
o_LOCKED=pll_locked, i_RST=self._r_pll_reset.storage,
51+
o_LOCKED=pll_locked, i_RST=self._pll_reset.storage,
5252

53-
i_DADDR=self._r_pll_adr.storage,
54-
o_DO=self._r_pll_dat_r.status,
55-
i_DI=self._r_pll_dat_w.storage,
56-
i_DEN=self._r_pll_read.re | self._r_pll_write.re,
57-
i_DWE=self._r_pll_write.re,
53+
i_DADDR=self._pll_adr.storage,
54+
o_DO=self._pll_dat_r.status,
55+
i_DI=self._pll_dat_w.storage,
56+
i_DEN=self._pll_read.re | self._pll_write.re,
57+
i_DWE=self._pll_write.re,
5858
o_DRDY=pll_drdy,
5959
i_DCLK=ClockSignal())
6060

@@ -67,7 +67,7 @@ def __init__(self, pads):
6767
Instance("BUFG", i_I=pll_clk2, o_O=self._cd_pix.clk),
6868
MultiReg(locked_async, self.locked, "sys")
6969
]
70-
self.comb += self._r_locked.status.eq(self.locked)
70+
self.comb += self._locked.status.eq(self.locked)
7171

7272
# sychronize pix+pix2x reset
7373
pix_rst_n = 1

Diff for: ‎misoclib/video/dvisampler/datacapture.py

+13-13
Original file line numberDiff line numberDiff line change
@@ -7,10 +7,10 @@ def __init__(self, pad_p, pad_n, ntbits):
77
self.serdesstrobe = Signal()
88
self.d = Signal(10)
99

10-
self._r_dly_ctl = CSR(6)
11-
self._r_dly_busy = CSRStatus(2)
12-
self._r_phase = CSRStatus(2)
13-
self._r_phase_reset = CSR()
10+
self._dly_ctl = CSR(6)
11+
self._dly_busy = CSRStatus(2)
12+
self._phase = CSRStatus(2)
13+
self._phase_reset = CSR()
1414

1515
###
1616

@@ -163,21 +163,21 @@ def __init__(self, pad_p, pad_n, ntbits):
163163
]
164164

165165
self.comb += [
166-
self.do_delay_master_cal.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[0]),
167-
self.do_delay_master_rst.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[1]),
168-
self.do_delay_slave_cal.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[2]),
169-
self.do_delay_slave_rst.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[3]),
170-
self.do_delay_inc.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[4]),
171-
self.do_delay_dec.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[5]),
172-
self._r_dly_busy.status.eq(Cat(sys_delay_master_pending, sys_delay_slave_pending))
166+
self.do_delay_master_cal.i.eq(self._dly_ctl.re & self._dly_ctl.r[0]),
167+
self.do_delay_master_rst.i.eq(self._dly_ctl.re & self._dly_ctl.r[1]),
168+
self.do_delay_slave_cal.i.eq(self._dly_ctl.re & self._dly_ctl.r[2]),
169+
self.do_delay_slave_rst.i.eq(self._dly_ctl.re & self._dly_ctl.r[3]),
170+
self.do_delay_inc.i.eq(self._dly_ctl.re & self._dly_ctl.r[4]),
171+
self.do_delay_dec.i.eq(self._dly_ctl.re & self._dly_ctl.r[5]),
172+
self._dly_busy.status.eq(Cat(sys_delay_master_pending, sys_delay_slave_pending))
173173
]
174174

175175
# Phase detector control
176-
self.specials += MultiReg(Cat(too_late, too_early), self._r_phase.status)
176+
self.specials += MultiReg(Cat(too_late, too_early), self._phase.status)
177177
self.submodules.do_reset_lateness = PulseSynchronizer("sys", "pix2x")
178178
self.comb += [
179179
reset_lateness.eq(self.do_reset_lateness.o),
180-
self.do_reset_lateness.i.eq(self._r_phase_reset.re)
180+
self.do_reset_lateness.i.eq(self._phase_reset.re)
181181
]
182182

183183
# 5:10 deserialization

Diff for: ‎misoclib/video/dvisampler/dma.py

+12-12
Original file line numberDiff line numberDiff line change
@@ -15,19 +15,19 @@ def __init__(self, addr_bits, alignment_bits):
1515
self.address_valid = Signal()
1616
self.address_done = Signal()
1717

18-
self._r_status = CSRStorage(2, write_from_dev=True)
19-
self._r_address = CSRStorage(addr_bits + alignment_bits, alignment_bits=alignment_bits, write_from_dev=True)
18+
self._status = CSRStorage(2, write_from_dev=True)
19+
self._address = CSRStorage(addr_bits + alignment_bits, alignment_bits=alignment_bits, write_from_dev=True)
2020

2121
###
2222

2323
self.comb += [
24-
self.address.eq(self._r_address.storage),
25-
self.address_valid.eq(self._r_status.storage[0]),
26-
self._r_status.dat_w.eq(2),
27-
self._r_status.we.eq(self.address_done),
28-
self._r_address.dat_w.eq(self.address_reached),
29-
self._r_address.we.eq(self.address_done),
30-
self.ev_source.trigger.eq(self._r_status.storage[1])
24+
self.address.eq(self._address.storage),
25+
self.address_valid.eq(self._status.storage[0]),
26+
self._status.dat_w.eq(2),
27+
self._status.we.eq(self.address_done),
28+
self._address.dat_w.eq(self.address_reached),
29+
self._address.we.eq(self.address_done),
30+
self.ev_source.trigger.eq(self._status.storage[1])
3131
]
3232

3333
class _SlotArray(Module, AutoCSR):
@@ -66,7 +66,7 @@ def __init__(self, lasmim, nslots):
6666

6767
fifo_word_width = 24*bus_dw//32
6868
self.frame = Sink([("sof", 1), ("pixels", fifo_word_width)])
69-
self._r_frame_size = CSRStorage(bus_aw + alignment_bits, alignment_bits=alignment_bits)
69+
self._frame_size = CSRStorage(bus_aw + alignment_bits, alignment_bits=alignment_bits)
7070
self.submodules._slot_array = _SlotArray(nslots, bus_aw, alignment_bits)
7171
self.ev = self._slot_array.ev
7272

@@ -85,7 +85,7 @@ def __init__(self, lasmim, nslots):
8585
self.sync += [
8686
If(reset_words,
8787
current_address.eq(self._slot_array.address),
88-
mwords_remaining.eq(self._r_frame_size.storage)
88+
mwords_remaining.eq(self._frame_size.storage)
8989
).Elif(count_word,
9090
current_address.eq(current_address + 1),
9191
mwords_remaining.eq(mwords_remaining - 1)
@@ -138,4 +138,4 @@ def __init__(self, lasmim, nslots):
138138
)
139139

140140
def get_csrs(self):
141-
return [self._r_frame_size] + self._slot_array.get_csrs()
141+
return [self._frame_size] + self._slot_array.get_csrs()

Diff for: ‎misoclib/video/dvisampler/edid.py

+6-6
Original file line numberDiff line numberDiff line change
@@ -18,19 +18,19 @@
1818

1919
class EDID(Module, AutoCSR):
2020
def __init__(self, pads, default=_default_edid):
21-
self._r_hpd_notif = CSRStatus()
22-
self._r_hpd_en = CSRStorage()
21+
self._hpd_notif = CSRStatus()
22+
self._hpd_en = CSRStorage()
2323
self.specials.mem = Memory(8, 128, init=default)
2424

2525
###
2626

2727
# HPD
2828
if hasattr(pads, "hpd_notif"):
29-
self.specials += MultiReg(pads.hpd_notif, self._r_hpd_notif.status)
29+
self.specials += MultiReg(pads.hpd_notif, self._hpd_notif.status)
3030
else:
31-
self.comb += self._r_hpd_notif.status.eq(1)
31+
self.comb += self._hpd_notif.status.eq(1)
3232
if hasattr(pads, "hpd_en"):
33-
self.comb += pads.hpd_en.eq(self._r_hpd_en.storage)
33+
self.comb += pads.hpd_en.eq(self._hpd_en.storage)
3434

3535
# EDID
3636
scl_raw = Signal()
@@ -186,4 +186,4 @@ def __init__(self, pads, default=_default_edid):
186186

187187
for state in fsm.actions.keys():
188188
fsm.act(state, If(start, NextState("RCV_ADDRESS")))
189-
fsm.act(state, If(~self._r_hpd_en.storage, NextState("WAIT_START")))
189+
fsm.act(state, If(~self._hpd_en.storage, NextState("WAIT_START")))

Diff for: ‎misoclib/video/dvisampler/wer.py

+3-3
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@
88
class WER(Module, AutoCSR):
99
def __init__(self, period_bits=24):
1010
self.data = Signal(10)
11-
self._r_update = CSR()
12-
self._r_value = CSRStatus(period_bits)
11+
self._update = CSR()
12+
self._value = CSRStatus(period_bits)
1313

1414
###
1515

@@ -56,4 +56,4 @@ def __init__(self, period_bits=24):
5656
self.sync += If(self.ps_counter.o, wer_counter_sys.eq(wer_counter_r))
5757

5858
# register interface
59-
self.sync += If(self._r_update.re, self._r_value.status.eq(wer_counter_sys))
59+
self.sync += If(self._update.re, self._value.status.eq(wer_counter_sys))

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