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remove use of _r prefix on CSRs
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enjoy-digital committed Apr 2, 2015
1 parent 696819c commit b437dc3
Showing 9 changed files with 66 additions and 66 deletions.
8 changes: 4 additions & 4 deletions misoclib/tools/litescope/frontend/io.py
Original file line number Diff line number Diff line change
@@ -3,8 +3,8 @@
class LiteScopeIO(Module, AutoCSR):
def __init__(self, dw):
self.dw = dw
self._r_i = CSRStatus(dw)
self._r_o = CSRStorage(dw)
self._i = CSRStatus(dw)
self._o = CSRStorage(dw)

self.i = self._r_i.status
self.o = self._r_o.storage
self.i = self._i.status
self.o = self._o.storage
8 changes: 4 additions & 4 deletions misoclib/video/dvisampler/analysis.py
Original file line number Diff line number Diff line change
@@ -120,7 +120,7 @@ def __init__(self, word_width):
self.frame = Source(word_layout)
self.busy = Signal()

self._r_overflow = CSR()
self._overflow = CSR()

###

@@ -194,11 +194,11 @@ def __init__(self, word_width):

overflow_mask = Signal()
self.comb += [
self._r_overflow.w.eq(sys_overflow & ~overflow_mask),
self.overflow_reset.i.eq(self._r_overflow.re)
self._overflow.w.eq(sys_overflow & ~overflow_mask),
self.overflow_reset.i.eq(self._overflow.re)
]
self.sync += \
If(self._r_overflow.re,
If(self._overflow.re,
overflow_mask.eq(1)
).Elif(self.overflow_reset_ack.o,
overflow_mask.eq(0)
4 changes: 2 additions & 2 deletions misoclib/video/dvisampler/chansync.py
Original file line number Diff line number Diff line change
@@ -42,7 +42,7 @@ def __init__(self, nchan=3, depth=8):
self.valid_i = Signal()
self.chan_synced = Signal()

self._r_channels_synced = CSRStatus()
self._channels_synced = CSRStatus()

lst_control = []
all_control = Signal()
@@ -85,7 +85,7 @@ def __init__(self, nchan=3, depth=8):
)
)
)
self.specials += MultiReg(self.chan_synced, self._r_channels_synced.status)
self.specials += MultiReg(self.chan_synced, self._channels_synced.status)

class _TB(Module):
def __init__(self, test_seq_it):
8 changes: 4 additions & 4 deletions misoclib/video/dvisampler/charsync.py
Original file line number Diff line number Diff line change
@@ -11,8 +11,8 @@ def __init__(self, required_controls=8):
self.synced = Signal()
self.data = Signal(10)

self._r_char_synced = CSRStatus()
self._r_ctl_pos = CSRStatus(bits_for(9))
self._char_synced = CSRStatus()
self._ctl_pos = CSRStatus(bits_for(9))

###

@@ -47,7 +47,7 @@ def __init__(self, required_controls=8):
),
previous_control_position.eq(control_position)
]
self.specials += MultiReg(self.synced, self._r_char_synced.status)
self.specials += MultiReg(word_sel, self._r_ctl_pos.status)
self.specials += MultiReg(self.synced, self._char_synced.status)
self.specials += MultiReg(word_sel, self._ctl_pos.status)

self.sync.pix += self.data.eq(raw >> word_sel)
36 changes: 18 additions & 18 deletions misoclib/video/dvisampler/clocking.py
Original file line number Diff line number Diff line change
@@ -4,16 +4,16 @@

class Clocking(Module, AutoCSR):
def __init__(self, pads):
self._r_pll_reset = CSRStorage(reset=1)
self._r_locked = CSRStatus()
self._pll_reset = CSRStorage(reset=1)
self._locked = CSRStatus()

# DRP
self._r_pll_adr = CSRStorage(5)
self._r_pll_dat_r = CSRStatus(16)
self._r_pll_dat_w = CSRStorage(16)
self._r_pll_read = CSR()
self._r_pll_write = CSR()
self._r_pll_drdy = CSRStatus()
self._pll_adr = CSRStorage(5)
self._pll_dat_r = CSRStatus(16)
self._pll_dat_w = CSRStorage(16)
self._pll_read = CSR()
self._pll_write = CSR()
self._pll_drdy = CSRStatus()

self.locked = Signal()
self.serdesstrobe = Signal()
@@ -32,10 +32,10 @@ def __init__(self, pads):
pll_clk1 = Signal()
pll_clk2 = Signal()
pll_drdy = Signal()
self.sync += If(self._r_pll_read.re | self._r_pll_write.re,
self._r_pll_drdy.status.eq(0)
self.sync += If(self._pll_read.re | self._pll_write.re,
self._pll_drdy.status.eq(0)
).Elif(pll_drdy,
self._r_pll_drdy.status.eq(1)
self._pll_drdy.status.eq(1)
)
self.specials += Instance("PLL_ADV",
p_CLKFBOUT_MULT=10,
@@ -48,13 +48,13 @@ def __init__(self, pads):
i_CLKIN1=clk_se,
o_CLKOUT0=pll_clk0, o_CLKOUT1=pll_clk1, o_CLKOUT2=pll_clk2,
o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbout,
o_LOCKED=pll_locked, i_RST=self._r_pll_reset.storage,
o_LOCKED=pll_locked, i_RST=self._pll_reset.storage,

i_DADDR=self._r_pll_adr.storage,
o_DO=self._r_pll_dat_r.status,
i_DI=self._r_pll_dat_w.storage,
i_DEN=self._r_pll_read.re | self._r_pll_write.re,
i_DWE=self._r_pll_write.re,
i_DADDR=self._pll_adr.storage,
o_DO=self._pll_dat_r.status,
i_DI=self._pll_dat_w.storage,
i_DEN=self._pll_read.re | self._pll_write.re,
i_DWE=self._pll_write.re,
o_DRDY=pll_drdy,
i_DCLK=ClockSignal())

@@ -67,7 +67,7 @@ def __init__(self, pads):
Instance("BUFG", i_I=pll_clk2, o_O=self._cd_pix.clk),
MultiReg(locked_async, self.locked, "sys")
]
self.comb += self._r_locked.status.eq(self.locked)
self.comb += self._locked.status.eq(self.locked)

# sychronize pix+pix2x reset
pix_rst_n = 1
26 changes: 13 additions & 13 deletions misoclib/video/dvisampler/datacapture.py
Original file line number Diff line number Diff line change
@@ -7,10 +7,10 @@ def __init__(self, pad_p, pad_n, ntbits):
self.serdesstrobe = Signal()
self.d = Signal(10)

self._r_dly_ctl = CSR(6)
self._r_dly_busy = CSRStatus(2)
self._r_phase = CSRStatus(2)
self._r_phase_reset = CSR()
self._dly_ctl = CSR(6)
self._dly_busy = CSRStatus(2)
self._phase = CSRStatus(2)
self._phase_reset = CSR()

###

@@ -163,21 +163,21 @@ def __init__(self, pad_p, pad_n, ntbits):
]

self.comb += [
self.do_delay_master_cal.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[0]),
self.do_delay_master_rst.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[1]),
self.do_delay_slave_cal.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[2]),
self.do_delay_slave_rst.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[3]),
self.do_delay_inc.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[4]),
self.do_delay_dec.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[5]),
self._r_dly_busy.status.eq(Cat(sys_delay_master_pending, sys_delay_slave_pending))
self.do_delay_master_cal.i.eq(self._dly_ctl.re & self._dly_ctl.r[0]),
self.do_delay_master_rst.i.eq(self._dly_ctl.re & self._dly_ctl.r[1]),
self.do_delay_slave_cal.i.eq(self._dly_ctl.re & self._dly_ctl.r[2]),
self.do_delay_slave_rst.i.eq(self._dly_ctl.re & self._dly_ctl.r[3]),
self.do_delay_inc.i.eq(self._dly_ctl.re & self._dly_ctl.r[4]),
self.do_delay_dec.i.eq(self._dly_ctl.re & self._dly_ctl.r[5]),
self._dly_busy.status.eq(Cat(sys_delay_master_pending, sys_delay_slave_pending))
]

# Phase detector control
self.specials += MultiReg(Cat(too_late, too_early), self._r_phase.status)
self.specials += MultiReg(Cat(too_late, too_early), self._phase.status)
self.submodules.do_reset_lateness = PulseSynchronizer("sys", "pix2x")
self.comb += [
reset_lateness.eq(self.do_reset_lateness.o),
self.do_reset_lateness.i.eq(self._r_phase_reset.re)
self.do_reset_lateness.i.eq(self._phase_reset.re)
]

# 5:10 deserialization
24 changes: 12 additions & 12 deletions misoclib/video/dvisampler/dma.py
Original file line number Diff line number Diff line change
@@ -15,19 +15,19 @@ def __init__(self, addr_bits, alignment_bits):
self.address_valid = Signal()
self.address_done = Signal()

self._r_status = CSRStorage(2, write_from_dev=True)
self._r_address = CSRStorage(addr_bits + alignment_bits, alignment_bits=alignment_bits, write_from_dev=True)
self._status = CSRStorage(2, write_from_dev=True)
self._address = CSRStorage(addr_bits + alignment_bits, alignment_bits=alignment_bits, write_from_dev=True)

###

self.comb += [
self.address.eq(self._r_address.storage),
self.address_valid.eq(self._r_status.storage[0]),
self._r_status.dat_w.eq(2),
self._r_status.we.eq(self.address_done),
self._r_address.dat_w.eq(self.address_reached),
self._r_address.we.eq(self.address_done),
self.ev_source.trigger.eq(self._r_status.storage[1])
self.address.eq(self._address.storage),
self.address_valid.eq(self._status.storage[0]),
self._status.dat_w.eq(2),
self._status.we.eq(self.address_done),
self._address.dat_w.eq(self.address_reached),
self._address.we.eq(self.address_done),
self.ev_source.trigger.eq(self._status.storage[1])
]

class _SlotArray(Module, AutoCSR):
@@ -66,7 +66,7 @@ def __init__(self, lasmim, nslots):

fifo_word_width = 24*bus_dw//32
self.frame = Sink([("sof", 1), ("pixels", fifo_word_width)])
self._r_frame_size = CSRStorage(bus_aw + alignment_bits, alignment_bits=alignment_bits)
self._frame_size = CSRStorage(bus_aw + alignment_bits, alignment_bits=alignment_bits)
self.submodules._slot_array = _SlotArray(nslots, bus_aw, alignment_bits)
self.ev = self._slot_array.ev

@@ -85,7 +85,7 @@ def __init__(self, lasmim, nslots):
self.sync += [
If(reset_words,
current_address.eq(self._slot_array.address),
mwords_remaining.eq(self._r_frame_size.storage)
mwords_remaining.eq(self._frame_size.storage)
).Elif(count_word,
current_address.eq(current_address + 1),
mwords_remaining.eq(mwords_remaining - 1)
@@ -138,4 +138,4 @@ def __init__(self, lasmim, nslots):
)

def get_csrs(self):
return [self._r_frame_size] + self._slot_array.get_csrs()
return [self._frame_size] + self._slot_array.get_csrs()
12 changes: 6 additions & 6 deletions misoclib/video/dvisampler/edid.py
Original file line number Diff line number Diff line change
@@ -18,19 +18,19 @@

class EDID(Module, AutoCSR):
def __init__(self, pads, default=_default_edid):
self._r_hpd_notif = CSRStatus()
self._r_hpd_en = CSRStorage()
self._hpd_notif = CSRStatus()
self._hpd_en = CSRStorage()
self.specials.mem = Memory(8, 128, init=default)

###

# HPD
if hasattr(pads, "hpd_notif"):
self.specials += MultiReg(pads.hpd_notif, self._r_hpd_notif.status)
self.specials += MultiReg(pads.hpd_notif, self._hpd_notif.status)
else:
self.comb += self._r_hpd_notif.status.eq(1)
self.comb += self._hpd_notif.status.eq(1)
if hasattr(pads, "hpd_en"):
self.comb += pads.hpd_en.eq(self._r_hpd_en.storage)
self.comb += pads.hpd_en.eq(self._hpd_en.storage)

# EDID
scl_raw = Signal()
@@ -186,4 +186,4 @@ def __init__(self, pads, default=_default_edid):

for state in fsm.actions.keys():
fsm.act(state, If(start, NextState("RCV_ADDRESS")))
fsm.act(state, If(~self._r_hpd_en.storage, NextState("WAIT_START")))
fsm.act(state, If(~self._hpd_en.storage, NextState("WAIT_START")))
6 changes: 3 additions & 3 deletions misoclib/video/dvisampler/wer.py
Original file line number Diff line number Diff line change
@@ -8,8 +8,8 @@
class WER(Module, AutoCSR):
def __init__(self, period_bits=24):
self.data = Signal(10)
self._r_update = CSR()
self._r_value = CSRStatus(period_bits)
self._update = CSR()
self._value = CSRStatus(period_bits)

###

@@ -56,4 +56,4 @@ def __init__(self, period_bits=24):
self.sync += If(self.ps_counter.o, wer_counter_sys.eq(wer_counter_r))

# register interface
self.sync += If(self._r_update.re, self._r_value.status.eq(wer_counter_sys))
self.sync += If(self._update.re, self._value.status.eq(wer_counter_sys))

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