m-labs · Apr 5, 2015 · Apr 5, 2015
Showing with 15 additions and 13 deletions.

+2 −2 examples/basic/two_dividers.py

+2 −2 migen/fhdl/decorators.py

+2 −0 migen/fhdl/std.py

+3 −3 migen/genlib/fifo.py

+6 −6 migen/genlib/misc.py
diff --git a/examples/basic/two_dividers.py b/examples/basic/two_dividers.py
@@ -2,8 +2,8 @@
 from migen.fhdl import verilog
 from migen.genlib import divider
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class Example(Module):
 	def __init__(self, width):
 		d1 = divider.Divider(width)

diff --git a/migen/fhdl/decorators.py b/migen/fhdl/decorators.py
@@ -48,11 +48,11 @@ def __call__(self, victim):
 
 	@classmethod
 	def adhoc(cls, i, *args, **kwargs):
-		warnings.warn("deprecated, use the plain transformer", DeprecationWarning)
+		warnings.warn("deprecated, use the plain transformer", DeprecationWarning, 2)
 		return cls(*args, **kwargs)(i)
 
 def DecorateModule(transformer, *args, **kwargs):
-	warnings.warn("deprecated, use the plain transformer", DeprecationWarning)
+	warnings.warn("deprecated, use the plain transformer", DeprecationWarning, 2)
 	return transformer.__self__(*args, **kwargs)
 
 class ControlInserter(ModuleTransformer):

diff --git a/migen/fhdl/std.py b/migen/fhdl/std.py
@@ -3,3 +3,5 @@
 from migen.fhdl.specials import TSTriple, Instance, Memory
 from migen.fhdl.bitcontainer import log2_int, bits_for, flen, fiter, fslice, freversed
 from migen.fhdl.decorators import DecorateModule, InsertCE, InsertReset, RenameClockDomains
+from migen.fhdl.decorators import (CEInserter, ResetInserter,
+	ClockDomainsRenamer, ModuleTransformer)
diff --git a/migen/genlib/fifo.py b/migen/genlib/fifo.py
@@ -158,7 +158,7 @@ class AsyncFIFO(Module, _FIFOInterface):
 	"""Asynchronous FIFO (first in, first out)
 
 	Read and write interfaces are accessed from different clock domains,
-	named `read` and `write`. Use `RenameClockDomains` to rename to
+	named `read` and `write`. Use `ClockDomainsRenamer` to rename to
 	other names.
 
 	{interface}
@@ -172,8 +172,8 @@ def __init__(self, width_or_layout, depth):
 
 		depth_bits = log2_int(depth, True)
 
-		produce = RenameClockDomains(GrayCounter(depth_bits+1), "write")
-		consume = RenameClockDomains(GrayCounter(depth_bits+1), "read")
+		produce = ClockDomainsRenamer("write")(GrayCounter(depth_bits+1))
+		consume = ClockDomainsRenamer("read")(GrayCounter(depth_bits+1))
 		self.submodules += produce, consume
 		self.comb += [
 			produce.ce.eq(self.writable & self.we),

diff --git a/migen/genlib/misc.py b/migen/genlib/misc.py
@@ -86,24 +86,24 @@ def get_cond(e):
 	sync.append(counterlogic)
 	return sync
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class FlipFlop(Module):
 	def __init__(self, *args, **kwargs):
 		self.d = Signal(*args, **kwargs)
 		self.q = Signal(*args, **kwargs)
 		self.sync += self.q.eq(self.d)
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class Counter(Module):
 	def __init__(self, *args, increment=1, **kwargs):
 		self.value = Signal(*args, **kwargs)
 		self.width = flen(self.value)
 		self.sync += self.value.eq(self.value+increment)
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class Timeout(Module):
 	def __init__(self, length):
 		self.reached = Signal()