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targets/kc705: enable Ethernet core
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sbourdeauducq committed Apr 10, 2015
1 parent 88e0aae commit b492aad
Showing 1 changed file with 4 additions and 4 deletions.
8 changes: 4 additions & 4 deletions soc/targets/artiq_kc705.py
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@

from misoclib.com import gpio
from misoclib.soc import mem_decoder
from targets.kc705 import BaseSoC
from targets.kc705 import MiniSoC

from artiq.gateware import amp, rtio, ad9858, nist_qc1

@@ -28,15 +28,15 @@ def __init__(self, platform, rtio_internal_clk):
o_O=self.cd_rtio.clk)


class _Peripherals(BaseSoC):
class _Peripherals(MiniSoC):
csr_map = {
"rtio": None, # mapped on Wishbone instead
"rtiocrg": 13
}
csr_map.update(BaseSoC.csr_map)
csr_map.update(MiniSoC.csr_map)

def __init__(self, platform, cpu_type="or1k", **kwargs):
BaseSoC.__init__(self, platform,
MiniSoC.__init__(self, platform,
cpu_type=cpu_type, **kwargs)
platform.add_extension(nist_qc1.fmc_adapter_io)

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