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liteeth: adapt to new ModuleTransformer
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sbourdeauducq committed Apr 10, 2015
1 parent ea613cd commit 603a4ef
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion misoclib/com/liteeth/mac/frontend/wishbone.py
Original file line number Diff line number Diff line change
@@ -23,7 +23,7 @@ def __init__(self, dw, nrxslots=2, ntxslots=2):
wb_rx_sram_ifs = [wishbone.SRAM(self.sram.writer.mems[n], read_only=True)
for n in range(nrxslots)]
# TODO: FullMemoryWE should move to Mibuild
wb_tx_sram_ifs = [FullMemoryWE(wishbone.SRAM(self.sram.reader.mems[n], read_only=False))
wb_tx_sram_ifs = [FullMemoryWE()(wishbone.SRAM(self.sram.reader.mems[n], read_only=False))
for n in range(ntxslots)]
wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs

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