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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: 8b41ab3a5ffc
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Apr 6, 2015

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    176b924 View commit details
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Showing with 2 additions and 2 deletions.
  1. +1 −1 make.py
  2. +1 −1 misoclib/soc/sdram.py
2 changes: 1 addition & 1 deletion make.py
Original file line number Diff line number Diff line change
@@ -81,7 +81,7 @@ def _get_args():
if args.external:
platform.soc_ext_path = os.path.abspath(args.external)

build_name = top_class.__name__.lower() + "-" + platform_name
build_name = args.target + "-" + top_class.__name__.lower() + "-" + platform_name
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs)
soc.finalize()
2 changes: 1 addition & 1 deletion misoclib/soc/sdram.py
Original file line number Diff line number Diff line change
@@ -61,7 +61,7 @@ def register_sdram_phy(self, phy):
from mibuild.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
from migen.fhdl.simplify import FullMemoryWE
self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master()))
self.submodules.wishbone2lasmi = FullMemoryWE()(wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master()))
else:
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master())
self.register_mem("main_ram", self.mem_map["main_ram"], self.wishbone2lasmi.wishbone, main_ram_size)